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twine: avoid TwinePool::lookup

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This commit is contained in:
Emil J. Tywoniak 2026-06-16 22:57:13 +02:00
parent 4061593ce5
commit 3a5f5c77bf
23 changed files with 277 additions and 259 deletions
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31
kernel/rtlil.cc
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@ -209,7 +209,7 @@ struct IdStringCollector {
}
void trace(const RTLIL::Cell &cell) {
trace_named(cell);
trace(cell.type);
trace(cell.type_impl);
trace_keys(cell.connections_);
trace_keys(cell.parameters);
}
@ -1536,14 +1536,14 @@ const RTLIL::Module *RTLIL::Design::module(TwineRef id) const {
RTLIL::Module *RTLIL::Design::module(TwineRef id) {
return modules_.count(id) ? modules_.at(id) : NULL;
}
const RTLIL::Module *RTLIL::Design::module(IdString id) const {
TwineRef r = twines.lookup(id.str());
return r == Twine::Null ? NULL : module(r);
}
RTLIL::Module *RTLIL::Design::module(IdString id) {
TwineRef r = twines.lookup(id.str());
return r == Twine::Null ? NULL : module(r);
}
// const RTLIL::Module *RTLIL::Design::module(IdString id) const {
// TwineRef r = twines.lookup(id.str());
// return r == Twine::Null ? NULL : module(r);
// }
// RTLIL::Module *RTLIL::Design::module(IdString id) {
// TwineRef r = twines.lookup(id.str());
// return r == Twine::Null ? NULL : module(r);
// }
RTLIL::Module *RTLIL::Design::top_module() const
{
@ -5168,7 +5168,7 @@ bool RTLIL::Cell::input(TwineRef portname) const
if (yosys_celltypes.cell_known(type_impl))
return yosys_celltypes.cell_input(type_impl, portname);
if (module && module->design) {
RTLIL::Module *m = module->design->module(type);
RTLIL::Module *m = module->design->module(type_impl);
RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
return w && w->port_input;
}
@ -5224,7 +5224,7 @@ const RTLIL::Const &RTLIL::Cell::getParam(IdString paramname) const
if (it != parameters.end())
return it->second;
if (module && module->design) {
RTLIL::Module *m = module->design->module(type);
RTLIL::Module *m = module->design->module(type_impl);
if (m)
return m->parameter_default_values.at(paramname);
}
@ -6586,6 +6586,9 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
sigspec_parse_split(tokens, str, ',');
sig = RTLIL::SigSpec();
std::optional<TwineSearch> search;
if (module)
search.emplace(&module->design->twines);
for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
{
std::string netname = tokens[tokidx];
@ -6609,7 +6612,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
if (netname[0] != '$' && netname[0] != '\\')
netname = "\\" + netname;
if (module->design->twines.lookup(netname) == Twine::Null) {
if (search->find(netname) == Twine::Null) {
size_t indices_pos = netname.size()-1;
if (indices_pos > 2 && netname[indices_pos] == ']')
{
@ -6627,12 +6630,12 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
}
{
TwineRef wid = module->design->twines.lookup(netname);
TwineRef wid = search->find(netname);
if (wid == Twine::Null || module->wires_.count(wid) == 0)
return false;
}
RTLIL::Wire *wire = module->wire(module->design->twines.lookup(netname));
RTLIL::Wire *wire = module->wire(search->find(netname));
if (!indices.empty()) {
std::vector<std::string> index_tokens;
sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');