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twine: avoid TwinePool::lookup
This commit is contained in:
Emil J. Tywoniak
parent
4061593ce5
commit
3a5f5c77bf
23 changed files with 277 additions and 259 deletions
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@ -1160,7 +1160,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
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module->design = design;
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module->ast = nullptr;
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module->meta_->name = design->twines.add(Twine{ast->str});
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module->meta_->name = design->twines.add(std::string{ast->str});
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set_src_attr(module, ast);
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module->set_bool_attribute(ID::cells_not_processed);
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@ -1376,7 +1376,7 @@ AST_INTERNAL::process_and_replace_module(RTLIL::Design *design,
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<< counter;
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++counter;
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design->rename(old_module, design->twines.add(Twine{new_name.str()}));
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design->rename(old_module, design->twines.add(std::string{new_name.str()}));
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old_module->set_bool_attribute(ID::to_delete);
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// Check if the module was the top module. If it was, we need to remove
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@ -1484,7 +1484,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
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if (defer_local)
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child->str = "$abstract" + child->str;
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TwineRef mod_name = design->twines.lookup(child->str);
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TwineRef mod_name = TwineSearch(&design->twines).find(child->str);
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if (design->has(mod_name)) {
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RTLIL::Module *existing_mod = design->module(mod_name);
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if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
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@ -1611,8 +1611,9 @@ bool AstModule::reprocess_if_necessary(RTLIL::Design *design)
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std::string modname = cell->get_string_attribute(ID::reprocess_after);
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if (modname.empty())
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continue;
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TwineRef mod_ref = design->twines.lookup(modname);
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TwineRef abstract_ref = design->twines.lookup("$abstract" + modname);
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TwineSearch search(&design->twines);
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TwineRef mod_ref = search.find(modname);
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TwineRef abstract_ref = search.find("$abstract" + modname);
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if (design->module(mod_ref) || design->module(abstract_ref)) {
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log("Reprocessing module %s because instantiated module %s has become available.\n",
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design->twines.str(meta_->name).c_str(), RTLIL::unescape_id(modname));
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@ -1661,7 +1662,8 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
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std::pair<std::string,std::string> res = split_modport_from_type(ch->str);
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std::string interface_type = res.first;
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std::string interface_modport = res.second; // Is "", if no modport
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if (design->module(interface_type) != nullptr) {
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TwineRef interface_type_ref = TwineSearch(&design->twines).find(interface_type);
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if (design->module(interface_type_ref) != nullptr) {
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// Add a cell to the module corresponding to the interface port such that
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// it can further propagated down if needed:
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auto celltype_for_intf = std::make_unique<AstNode>(loc, AST_CELLTYPE);
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@ -1671,7 +1673,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
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new_ast->children.push_back(std::move(cell_for_intf));
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// Get all members of this non-overridden dummy interface instance:
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RTLIL::Module *intfmodule = design->module(interface_type); // All interfaces should at this point in time (assuming
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RTLIL::Module *intfmodule = design->module(interface_type_ref); // All interfaces should at this point in time (assuming
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// reprocess_module is called from the hierarchy pass) be
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// present in design->modules_
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AstModule *ast_module_of_interface = (AstModule*)intfmodule;
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@ -1718,10 +1720,11 @@ TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RT
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if (has_interfaces)
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new_modname += "$interfaces$" + interf_info;
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TwineRef new_modname_ref = design->twines.lookup(new_modname);
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TwineSearch search(&design->twines);
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TwineRef new_modname_ref = search.find(new_modname);
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if (!design->has(new_modname_ref)) {
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if (!new_ast) {
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TwineRef modname_ref = design->twines.lookup(modname);
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TwineRef modname_ref = search.find(modname);
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auto mod = dynamic_cast<AstModule*>(design->module(modname_ref));
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new_ast = mod->ast->clone();
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}
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@ -1745,13 +1748,14 @@ TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RT
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}
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process_module(design, new_ast.get(), false);
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design->module(modname)->check();
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TwineRef new_ref = TwineSearch(&design->twines).find(modname);
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design->module(new_ref)->check();
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RTLIL::Module* mod = design->module(modname);
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RTLIL::Module* mod = design->module(new_ref);
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// Now that the interfaces have been exploded, we can delete the dummy port related to every interface.
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for(auto &intf : interfaces) {
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TwineRef intf_name = design->twines.lookup(design->twines.str(intf.first));
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TwineRef intf_name = intf.first;
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if(mod->wire(intf_name) != nullptr) {
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// Normally, removing wires would be batched together as it's an
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// expensive operation, however, in this case doing so would mean
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@ -1782,7 +1786,7 @@ TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RT
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log("Found cached RTLIL representation for module `%s'.\n", modname);
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}
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return design->twines.add(Twine{modname});
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return design->twines.add(std::string{modname});
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}
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// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
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@ -1793,7 +1797,7 @@ TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RT
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std::unique_ptr<AstNode> new_ast = NULL;
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std::string modname = derive_common(design, parameters, &new_ast, quiet);
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TwineRef modname_ref = design->twines.lookup(modname);
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TwineRef modname_ref = design->twines.add(std::string{modname});
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if (!design->has(modname_ref) && new_ast) {
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new_ast->str = modname;
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process_module(design, new_ast.get(), false, NULL, quiet);
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@ -1802,7 +1806,7 @@ TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RT
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log("Found cached RTLIL representation for module `%s'.\n", modname);
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}
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return design->twines.add(Twine{modname});
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return modname_ref;
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}
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static std::string serialize_param_value(const RTLIL::Const &val) {
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@ -1868,7 +1872,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
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if (parameters.size()) // not named_parameters to cover hierarchical defparams
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modname = derived_module_name(stripped_name, named_parameters);
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if (design->has(design->twines.lookup(modname)))
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if (design->has(TwineSearch(&design->twines).find(modname)))
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return modname;
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if (!quiet)
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@ -46,8 +46,8 @@ using namespace AST_INTERNAL;
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// helper function for creating RTLIL code for unary operations
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static RTLIL::SigSpec uniop2rtlil(AstNode *that, TwineRef type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
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{
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IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type);
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IdString name = stringf("%s$%s:%d$%d", current_module->design->twines.str(type).c_str(), RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{name.str()}), type);
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set_src_attr(cell, that);
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RTLIL::Wire *wire = current_module->addWire(Twine{Twine::Suffix{cell->meta_->name, "_Y"}}, result_width);
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@ -79,10 +79,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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}
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IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, TW::$pos);
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RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{name.str()}), TW::$pos);
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set_src_attr(cell, that);
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RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, width);
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RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{cell->name.str() + "_Y"}), width);
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set_src_attr(wire, that);
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wire->is_signed = that->is_signed;
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@ -105,8 +105,8 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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// helper function for creating RTLIL code for binary operations
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static RTLIL::SigSpec binop2rtlil(AstNode *that, TwineRef type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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{
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IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type);
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IdString name = stringf("%s$%s:%d$%d", current_module->design->twines.str(type).c_str(), RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{name.str()}), type);
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set_src_attr(cell, that);
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RTLIL::Wire *wire = current_module->addWire(Twine{Twine::Suffix{cell->meta_->name, "_Y"}}, result_width);
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@ -141,10 +141,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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std::stringstream sstr;
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sstr << "$ternary$" << RTLIL::encode_filename(*that->location.begin.filename) << ":" << that->location.begin.line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$mux);
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RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{sstr.str()}), TW::$mux);
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set_src_attr(cell, that);
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RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, left.size());
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RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{cell->name.str() + "_Y"}), left.size());
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set_src_attr(wire, that);
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wire->is_signed = that->is_signed;
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@ -178,7 +178,7 @@ static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
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to_add_kind, id.c_str(), existing_kind, location_str.c_str());
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};
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TwineRef id_tw = module->design->twines.lookup(id.str());
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TwineRef id_tw = TwineSearch(&module->design->twines).find(id.str());
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if (const RTLIL::Wire *wire = module->wire(id_tw))
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already_exists(wire, "signal");
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if (const RTLIL::Cell *cell = module->cell(id_tw))
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@ -355,7 +355,7 @@ struct AST_INTERNAL::ProcessGenerator
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LookaheadRewriter la_rewriter(always.get());
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// generate process and simple root case
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proc = current_module->addProcess(Twine{stringf("$proc$%s:%d$%d", RTLIL::encode_filename(*always->location.begin.filename), always->location.begin.line, autoidx++)});
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proc = current_module->addProcess(current_module->design->twines.add(std::string{stringf("$proc$%s:%d$%d", RTLIL::encode_filename(*always->location.begin.filename), always->location.begin.line, autoidx++)}));
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set_src_attr(proc, always.get());
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -500,14 +500,15 @@ struct AST_INTERNAL::ProcessGenerator
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continue;
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std::string wire_name;
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TwineSearch search(¤t_module->design->twines);
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do {
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wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
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chunk.wire->name, chunk.width+chunk.offset-1, chunk.offset);;
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if (chunk.wire->name.str().find('$') != std::string::npos)
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wire_name += stringf("$%d", autoidx++);
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} while (current_module->wire(current_module->design->twines.lookup(wire_name)) != nullptr);
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} while (current_module->wire(search.find(wire_name)) != nullptr);
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RTLIL::Wire *wire = current_module->addWire(Twine{wire_name}, chunk.width);
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RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{wire_name}), chunk.width);
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set_src_attr(wire, always.get());
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chunk.wire = wire;
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@ -820,7 +821,7 @@ struct AST_INTERNAL::ProcessGenerator
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std::stringstream sstr;
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sstr << ast->str << "$" << ast->location.begin.filename << ":" << ast->location.begin.line << "$" << (autoidx++);
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Wire *en = current_module->addWire(Twine{sstr.str() + "_EN"}, 1);
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Wire *en = current_module->addWire(current_module->design->twines.add(std::string{sstr.str() + "_EN"}), 1);
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set_src_attr(en, ast);
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proc->root_case.actions.push_back(SigSig(en, false));
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current_case->actions.push_back(SigSig(en, true));
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@ -838,7 +839,7 @@ struct AST_INTERNAL::ProcessGenerator
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}
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RTLIL::Const polarity = polarity_builder.build();
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RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$print);
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RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{sstr.str()}), TW::$print);
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set_src_attr(cell, ast);
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cell->setParam(ID::TRG_WIDTH, triggers.size());
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cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
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@ -918,7 +919,7 @@ struct AST_INTERNAL::ProcessGenerator
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if (GetSize(check) != 1)
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check = current_module->ReduceBool(NEW_TWINE, check);
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Wire *en = current_module->addWire(Twine{cellname.str() + "_EN"}, 1);
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Wire *en = current_module->addWire(current_module->design->twines.add(std::string{cellname.str() + "_EN"}), 1);
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set_src_attr(en, ast);
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proc->root_case.actions.push_back(SigSig(en, false));
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current_case->actions.push_back(SigSig(en, true));
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@ -936,7 +937,7 @@ struct AST_INTERNAL::ProcessGenerator
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}
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RTLIL::Const polarity = polarity_builder.build();
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RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, TW::$check);
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RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{cellname.str()}), TW::$check);
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set_src_attr(cell, ast);
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cell->set_bool_attribute(ID(keep));
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for (auto &attr : ast->attributes) {
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@ -984,7 +985,7 @@ struct AST_INTERNAL::ProcessGenerator
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set_src_attr(&action, child.get());
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action.memid = memid;
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action.address = child->children[0]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
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action.data = child->children[1]->genWidthRTLIL(current_module->memories[current_module->design->twines.lookup(memid)]->width, true, &subst_rvalue_map.stdmap());
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action.data = child->children[1]->genWidthRTLIL(current_module->memories[TwineSearch(¤t_module->design->twines).find(memid)]->width, true, &subst_rvalue_map.stdmap());
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action.enable = child->children[2]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
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RTLIL::Const orig_priority_mask = child->children[4]->bitsAsConst();
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RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx);
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@ -1477,7 +1478,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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// signals.
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RTLIL::IdString id = str;
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check_unique_id(current_module, id, this, "interface port");
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RTLIL::Wire *wire = current_module->addWire(Twine{id.str()}, 1);
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RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{id.str()}), 1);
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set_src_attr(wire, this);
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wire->start_offset = 0;
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wire->port_id = port_id;
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@ -1517,7 +1518,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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RTLIL::Const val = children[0]->bitsAsConst();
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RTLIL::IdString id = str;
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check_unique_id(current_module, id, this, "pwire");
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RTLIL::Wire *wire = current_module->addWire(Twine{id.str()}, GetSize(val));
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RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{id.str()}), GetSize(val));
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current_module->connect(wire, val);
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wire->is_signed = children[0]->is_signed;
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@ -1542,7 +1543,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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RTLIL::IdString id = str;
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check_unique_id(current_module, id, this, "signal");
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RTLIL::Wire *wire = current_module->addWire(Twine{id.str()}, range_left - range_right + 1);
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RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{id.str()}), range_left - range_right + 1);
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set_src_attr(wire, this);
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wire->start_offset = range_right;
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wire->port_id = port_id;
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@ -1573,7 +1574,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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input_error("Memory `%s' with non-constant width or size!\n", str);
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check_unique_id(current_module, RTLIL::IdString(str), this, "memory");
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RTLIL::Memory *memory = current_module->addMemory(Twine{str});
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RTLIL::Memory *memory = current_module->addMemory(current_module->design->twines.add(std::string{str}));
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set_src_attr(memory, this);
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memory->width = children[0]->range_left - children[0]->range_right + 1;
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if (children[1]->range_right < children[1]->range_left) {
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@ -1628,8 +1629,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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log_assert(id2ast != nullptr);
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if (id2ast->type == AST_AUTOWIRE && current_module->wire(current_module->design->twines.lookup(str)) == nullptr) {
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RTLIL::Wire *wire = current_module->addWire(Twine{str});
|
||||
TwineSearch search(¤t_module->design->twines);
|
||||
TwineRef str_ref = search.find(str);
|
||||
|
||||
if (id2ast->type == AST_AUTOWIRE && current_module->wire(str_ref) == nullptr) {
|
||||
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{str}));
|
||||
str_ref = wire->name.ref();
|
||||
set_src_attr(wire, this);
|
||||
|
||||
// If we are currently processing a bind directive which wires up
|
||||
|
|
@ -1650,8 +1655,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
chunk = RTLIL::Const(id2ast->children[0]->bits);
|
||||
goto use_const_chunk;
|
||||
}
|
||||
else if ((id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wire(current_module->design->twines.lookup(str)) != nullptr) {
|
||||
RTLIL::Wire *current_wire = current_module->wire(current_module->design->twines.lookup(str));
|
||||
else if ((id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wire(str_ref) != nullptr) {
|
||||
RTLIL::Wire *current_wire = current_module->wire(str_ref);
|
||||
if (current_wire->get_bool_attribute(ID::is_interface))
|
||||
is_interface = true;
|
||||
// Ignore
|
||||
|
|
@ -1672,15 +1677,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
// with the individual signals:
|
||||
if (is_interface) {
|
||||
IdString dummy_wire_name = stringf("$dummywireforinterface%s", str);
|
||||
RTLIL::Wire *dummy_wire = current_module->wire(current_module->design->twines.lookup(dummy_wire_name.str()));
|
||||
RTLIL::Wire *dummy_wire = current_module->wire(search.find(dummy_wire_name.str()));
|
||||
if (!dummy_wire) {
|
||||
dummy_wire = current_module->addWire(Twine{dummy_wire_name.str()});
|
||||
dummy_wire = current_module->addWire(current_module->design->twines.add(std::string{dummy_wire_name.str()}));
|
||||
dummy_wire->set_bool_attribute(ID::is_interface);
|
||||
}
|
||||
return dummy_wire;
|
||||
}
|
||||
|
||||
wire = current_module->wire(current_module->design->twines.lookup(str));
|
||||
wire = current_module->wire(str_ref);
|
||||
chunk.wire = wire;
|
||||
chunk.width = wire->width;
|
||||
chunk.offset = 0;
|
||||
|
|
@ -2044,10 +2049,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
std::stringstream sstr;
|
||||
sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$memrd);
|
||||
RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{sstr.str()}), TW::$memrd);
|
||||
set_src_attr(cell, this);
|
||||
|
||||
RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_DATA"}, current_module->memories[current_module->design->twines.lookup(str)]->width);
|
||||
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{cell->name.str() + "_DATA"}), current_module->memories[TwineSearch(¤t_module->design->twines).find(str)]->width);
|
||||
set_src_attr(wire, this);
|
||||
|
||||
int mem_width, mem_size, addr_bits;
|
||||
|
|
@ -2084,7 +2089,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
SigSpec en_sig = children[2]->genRTLIL();
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$meminit_v2);
|
||||
RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{sstr.str()}), TW::$meminit_v2);
|
||||
set_src_attr(cell, this);
|
||||
|
||||
int mem_width, mem_size, addr_bits;
|
||||
|
|
@ -2098,12 +2103,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
SigSpec addr_sig = children[0]->genRTLIL();
|
||||
|
||||
cell->setPort(TW::ADDR, addr_sig);
|
||||
cell->setPort(TW::DATA, children[1]->genWidthRTLIL(current_module->memories[current_module->design->twines.lookup(str)]->width * num_words, true));
|
||||
cell->setPort(TW::DATA, children[1]->genWidthRTLIL(current_module->memories[TwineSearch(¤t_module->design->twines).find(str)]->width * num_words, true));
|
||||
cell->setPort(TW::EN, en_sig);
|
||||
|
||||
cell->parameters[ID::MEMID] = RTLIL::Const(str);
|
||||
cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
|
||||
cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[current_module->design->twines.lookup(str)]->width);
|
||||
cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[TwineSearch(¤t_module->design->twines).find(str)]->width);
|
||||
|
||||
cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
|
||||
}
|
||||
|
|
@ -2134,7 +2139,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (GetSize(check) != 1)
|
||||
check = current_module->ReduceBool(NEW_TWINE, check);
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, TW::$check);
|
||||
RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{cellname.str()}), TW::$check);
|
||||
set_src_attr(cell, this);
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
|
|
@ -2186,7 +2191,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
RTLIL::IdString id = str;
|
||||
check_unique_id(current_module, id, this, "cell");
|
||||
RTLIL::Cell *cell = current_module->addCell(Twine{id.str()}, Twine::Null);
|
||||
RTLIL::Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{id.str()}), Twine::Null);
|
||||
set_src_attr(cell, this);
|
||||
|
||||
for (auto it = children.begin(); it != children.end(); it++) {
|
||||
|
|
@ -2195,7 +2200,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
std::string type_str = child->str;
|
||||
if (flag_icells && type_str.size() >= 2 && type_str[0] == '\\' && type_str[1] == '$')
|
||||
type_str = type_str.substr(1);
|
||||
cell->type_impl = current_module->design->twines.add(Twine{type_str});
|
||||
cell->type_impl = current_module->design->twines.add(std::string{type_str});
|
||||
continue;
|
||||
}
|
||||
if (child->type == AST_PARASET) {
|
||||
|
|
@ -2234,7 +2239,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
// non-trivial signed nodes are indirected through
|
||||
// signed wires to enable sign extension
|
||||
RTLIL::IdString wire_name = NEW_ID;
|
||||
RTLIL::Wire *wire = current_module->addWire(Twine{wire_name.str()}, GetSize(sig));
|
||||
RTLIL::Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{wire_name.str()}), GetSize(sig));
|
||||
wire->is_signed = true;
|
||||
current_module->connect(wire, sig);
|
||||
sig = wire;
|
||||
|
|
@ -2243,9 +2248,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (child->str.size() == 0) {
|
||||
char buf[100];
|
||||
snprintf(buf, 100, "$%d", ++port_counter);
|
||||
cell->setPort(current_module->design->twines.add(Twine{std::string(buf)}), sig);
|
||||
cell->setPort(current_module->design->twines.add(std::string{std::string(buf)}), sig);
|
||||
} else {
|
||||
cell->setPort(current_module->design->twines.add(Twine{child->str}), sig);
|
||||
cell->setPort(current_module->design->twines.add(std::string{child->str}), sig);
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2357,8 +2362,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (width <= 0)
|
||||
input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str));
|
||||
|
||||
TwineRef _type = current_module->design->twines.add(Twine{str.substr(1)});
|
||||
Cell *cell = current_module->addCell(Twine{myid}, _type);
|
||||
TwineRef _type = current_module->design->twines.add(std::string{str});
|
||||
Cell *cell = current_module->addCell(current_module->design->twines.add(std::string{myid}), _type);
|
||||
set_src_attr(cell, this);
|
||||
cell->parameters[ID::WIDTH] = width;
|
||||
|
||||
|
|
@ -2369,7 +2374,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
cell->attributes[ID::reg] = attr->asAttrConst();
|
||||
}
|
||||
|
||||
Wire *wire = current_module->addWire(Twine{myid + "_wire"}, width);
|
||||
Wire *wire = current_module->addWire(current_module->design->twines.add(std::string{myid + "_wire"}), width);
|
||||
set_src_attr(wire, this);
|
||||
cell->setPort(TW::Y, wire);
|
||||
|
||||
|
|
|
|||
|
|
@ -704,7 +704,7 @@ void AST::set_simplify_design_context(const RTLIL::Design *design)
|
|||
// lookup the module with the given name in the current design context
|
||||
static const RTLIL::Module* lookup_module(const std::string &name)
|
||||
{
|
||||
return simplify_design_context->module(name);
|
||||
return simplify_design_context->module(TwineSearch(&simplify_design_context->twines).find(name));
|
||||
}
|
||||
|
||||
const RTLIL::Module* AstNode::lookup_cell_module()
|
||||
|
|
@ -1474,6 +1474,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
|
|||
module = lookup_cell_module();
|
||||
if (module) {
|
||||
size_t port_counter = 0;
|
||||
TwineSearch search(&module->design->twines);
|
||||
for (auto& child : children) {
|
||||
if (child->type != AST_ARGUMENT)
|
||||
continue;
|
||||
|
|
@ -1481,7 +1482,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
|
|||
// determine the full name of port this argument is connected to
|
||||
TwineRef port_name;
|
||||
if (child->str.size())
|
||||
port_name = module->design->twines.lookup(child->str);
|
||||
port_name = search.find(child->str);
|
||||
else {
|
||||
if (port_counter >= module->ports.size())
|
||||
input_error("Cell instance has more ports than the module!\n");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue