mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-02 05:59:31 +00:00
Code Activity

Progress in presentation

Browse source
This commit is contained in:
Clifford Wolf 2014-06-29 09:14:49 +02:00
parent 89c85cac41
commit 3a3f5d5923
2 changed files with 97 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

19
manual/presentation.tex
View file

@ -122,6 +122,25 @@ non-synthesis applications (such as formal equivialence checking) and
writing extensions to Yosys using the C++ API.
\end{frame}
\section{About me}
\begin{frame}{About me}
Hi! I'm Clifford Wolf.
\bigskip
I like writing open source software. For example:
\begin{itemize}
\item Yosys
\item OpenSCAD (now maintained by Marius Kintel)
\item SPL (a not very popular scripting language)
\item EmbedVM (a very simple colipler+vm for 8 bit micros)
\item Lib(X)SVF (a library to play SVF/XSVF files over JTAG, used at LHC)
\item ROCK Linux (inactive since 2010)
\end{itemize}
\bigskip
What do I do for a living? Ask me off the record..
\end{frame}
\section{Outline}
\begin{frame}{Outline}
Yosys is an Open Source Verilog synthesis tool, and more.