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Set more ports explicitly

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This commit is contained in:
Eddie Hung 2019-09-12 17:10:43 -07:00
parent a1123b095c
commit 3a39073302
2 changed files with 4 additions and 1 deletions
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techlibs/xilinx/dsp_map.v
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@ -25,7 +25,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
.OPMODEREG(0),
.PREG(0),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48")
.USE_SIMD("ONE48"),
.USE_DPORT("FALSE")
) _TECHMAP_REPLACE_ (
//Data path
.A({{5{A[24]}}, A}),