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Docs: Apply invert-helper where needed

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Krystine Sherwin 2024-05-11 10:40:54 +12:00
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docs/source/yosys_internals/flow/verilog_frontend.rst
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@ -10,7 +10,7 @@ is then passed to the AST frontend that converts it to RTLIL data, as
illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
.. figure:: /_images/internals/verilog_flow.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:Verilog_flow
Simplified Verilog to RTLIL data flow