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Docs: Apply invert-helper where needed

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Krystine Sherwin 2024-05-11 10:40:54 +12:00
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docs/source/yosys_internals/flow/control_and_data.rst
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@ -10,7 +10,7 @@ and generating the data for the next subsystem (see :numref:`Fig. %s
<fig:approach_flow>`).
.. figure:: /_images/internals/approach_flow.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:approach_flow
General data- and control-flow of a synthesis tool

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docs/source/yosys_internals/flow/overview.rst
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@ -42,7 +42,7 @@ possible it is key that (1) all passes operate on the same data structure
design in different stages of the synthesis.
.. figure:: /_images/internals/overview_flow.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:Overview_flow
Yosys simplified data flow (ellipses: data structures, rectangles:

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docs/source/yosys_internals/flow/verilog_frontend.rst
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@ -10,7 +10,7 @@ is then passed to the AST frontend that converts it to RTLIL data, as
illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
.. figure:: /_images/internals/verilog_flow.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:Verilog_flow
Simplified Verilog to RTLIL data flow