Docs: Apply invert-helper where needed

docs/source/yosys_internals/extending_yosys/extensions.rst

@@ -38,7 +38,7 @@ This document will focus on the much simpler version of RTLIL left after the
 commands :cmd:ref:`proc` and :cmd:ref:`memory` (or :yoscrypt:`memory -nomap`):
 
 .. figure:: /_images/internals/simplified_rtlil.*
-    :class: width-helper
+    :class: width-helper invert-helper
     :name: fig:Simplified_RTLIL
 
     Simplified RTLIL entity-relationship diagram without memories and processes
@@ -140,7 +140,7 @@ We'll do the same as before and format it as a a ``Yosys::Pass``.
 And if we look at the schematic for this new module we see the following:
 
 .. figure:: /_images/code_examples/extensions/test1.*
-   :class: width-helper
+   :class: width-helper invert-helper
 
    Output of ``yosys -m ./my_cmd.so -p 'test1; show'``
 

docs/source/yosys_internals/flow/control_and_data.rst

@@ -10,7 +10,7 @@ and generating the data for the next subsystem (see :numref:`Fig. %s
 <fig:approach_flow>`).
 
 .. figure:: /_images/internals/approach_flow.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:approach_flow
 
 	General data- and control-flow of a synthesis tool

docs/source/yosys_internals/flow/overview.rst

@@ -42,7 +42,7 @@ possible it is key that (1) all passes operate on the same data structure
 design in different stages of the synthesis.
 
 .. figure:: /_images/internals/overview_flow.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Overview_flow
 
 	Yosys simplified data flow (ellipses: data structures, rectangles:

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -10,7 +10,7 @@ is then passed to the AST frontend that converts it to RTLIL data, as
 illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
 
 .. figure:: /_images/internals/verilog_flow.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Verilog_flow
 
 	Simplified Verilog to RTLIL data flow

docs/source/yosys_internals/formats/rtlil_rep.rst

@@ -24,7 +24,7 @@ create an additional ``RTLIL::Design`` object and call the Verilog frontend with
 this other object to parse the cell library.
 
 .. figure:: /_images/internals/overview_rtlil.*
-	:class: width-helper
+	:class: width-helper invert-helper
 	:name: fig:Overview_RTLIL
 
 	Simplified RTLIL Entity-Relationship Diagram

docs/source/yosys_internals/techmap.rst

@@ -34,7 +34,7 @@ Mapping OR3X1
    :caption: :file:`red_or3x1_map.v`
 
 .. figure:: /_images/code_examples/techmap/red_or3x1.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/red_or3x1_test.ys
    :language: yoscrypt
@@ -61,7 +61,7 @@ Conditional techmap
 Example:
 
 .. figure:: /_images/code_examples/techmap/sym_mul.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/sym_mul_map.v
    :language: verilog
@@ -100,7 +100,7 @@ Scripting in map modules
 Example:
 
 .. figure:: /_images/code_examples/techmap/mymul.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/mymul_map.v
    :language: verilog
@@ -130,7 +130,7 @@ Handling constant inputs
 Example:
 
 .. figure:: /_images/code_examples/techmap/mulshift.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/mulshift_map.v
    :language: verilog
@@ -162,7 +162,7 @@ Handling shorted inputs
 Example:
 
 .. figure:: /_images/code_examples/techmap/addshift.*
-    :class: width-helper
+    :class: width-helper invert-helper
 
 .. literalinclude:: /code_examples/techmap/addshift_map.v
    :language: verilog