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Docs: Apply invert-helper where needed

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Krystine Sherwin 2024-05-11 10:40:54 +12:00
parent 9be7089f4f
commit 3a36612ec7
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17 changed files with 93 additions and 93 deletions
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8
docs/source/using_yosys/synthesis/cell_libs.rst
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@ -51,7 +51,7 @@ Loading the design
Our circuit now looks like this:
.. figure:: /_images/code_examples/intro/counter_00.*
:class: width-helper
:class: width-helper invert-helper
:name: counter-hierarchy
``counter`` after :cmd:ref:`hierarchy`
@ -66,7 +66,7 @@ Coarse-grain representation
:caption: :file:`counter.ys` - the high-level stuff
.. figure:: /_images/code_examples/intro/counter_01.*
:class: width-helper
:class: width-helper invert-helper
Coarse-grain representation of the ``counter`` module
@ -80,7 +80,7 @@ Logic gate mapping
:caption: :file:`counter.ys` - mapping to internal cell library
.. figure:: /_images/code_examples/intro/counter_02.*
:class: width-helper
:class: width-helper invert-helper
``counter`` after :cmd:ref:`techmap`
@ -111,7 +111,7 @@ Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
The final version of our ``counter`` module looks like this:
.. figure:: /_images/code_examples/intro/counter_03.*
:class: width-helper
:class: width-helper invert-helper
``counter`` after hardware cell mapping