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Docs: Apply invert-helper where needed

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Krystine Sherwin 2024-05-11 10:40:54 +12:00
parent 9be7089f4f
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17 changed files with 93 additions and 93 deletions
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8
docs/source/using_yosys/synthesis/cell_libs.rst
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@ -51,7 +51,7 @@ Loading the design
Our circuit now looks like this:
.. figure:: /_images/code_examples/intro/counter_00.*
:class: width-helper
:class: width-helper invert-helper
:name: counter-hierarchy
``counter`` after :cmd:ref:`hierarchy`
@ -66,7 +66,7 @@ Coarse-grain representation
:caption: :file:`counter.ys` - the high-level stuff
.. figure:: /_images/code_examples/intro/counter_01.*
:class: width-helper
:class: width-helper invert-helper
Coarse-grain representation of the ``counter`` module
@ -80,7 +80,7 @@ Logic gate mapping
:caption: :file:`counter.ys` - mapping to internal cell library
.. figure:: /_images/code_examples/intro/counter_02.*
:class: width-helper
:class: width-helper invert-helper
``counter`` after :cmd:ref:`techmap`
@ -111,7 +111,7 @@ Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
The final version of our ``counter`` module looks like this:
.. figure:: /_images/code_examples/intro/counter_03.*
:class: width-helper
:class: width-helper invert-helper
``counter`` after hardware cell mapping

40
docs/source/using_yosys/synthesis/extract.rst
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@ -23,7 +23,7 @@ Example code can be found in |code_examples/macc|_.
:lines: 1-2
.. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
:class: width-helper
:class: width-helper invert-helper
before :cmd:ref:`extract`
@ -32,7 +32,7 @@ Example code can be found in |code_examples/macc|_.
:lines: 6
.. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
:class: width-helper
:class: width-helper invert-helper
after :cmd:ref:`extract`
@ -49,20 +49,20 @@ Example code can be found in |code_examples/macc|_.
:caption: :file:`macc_simple_test_01.v`
.. figure:: /_images/code_examples/macc/macc_simple_test_01a.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/macc/macc_simple_test_01b.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_simple_test_02.v
:language: verilog
:caption: :file:`macc_simple_test_02.v`
.. figure:: /_images/code_examples/macc/macc_simple_test_02a.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/macc/macc_simple_test_02b.*
:class: width-helper
:class: width-helper invert-helper
The wrap-extract-unwrap method
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -149,10 +149,10 @@ Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
:caption: ``test1`` of :file:`macc_xilinx_test.v`
.. figure:: /_images/code_examples/macc/macc_xilinx_test1a.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
:language: verilog
@ -160,15 +160,15 @@ Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
:caption: ``test2`` of :file:`macc_xilinx_test.v`
.. figure:: /_images/code_examples/macc/macc_xilinx_test2a.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
:class: width-helper
:class: width-helper invert-helper
Wrapping in ``test1``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -176,12 +176,12 @@ Wrapping in ``test1``:
:end-before: end part c
.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
:class: width-helper
:class: width-helper invert-helper
Wrapping in ``test2``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -189,12 +189,12 @@ Wrapping in ``test2``:
:end-before: end part c
.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
:class: width-helper
:class: width-helper invert-helper
Extract in ``test1``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -202,12 +202,12 @@ Extract in ``test1``:
:end-before: end part d
.. figure:: /_images/code_examples/macc/macc_xilinx_test1d.*
:class: width-helper
:class: width-helper invert-helper
Extract in ``test2``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -215,12 +215,12 @@ Extract in ``test2``:
:end-before: end part d
.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
:class: width-helper
:class: width-helper invert-helper
Unwrap in ``test2``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -228,4 +228,4 @@ Unwrap in ``test2``:
:end-before: end part e
.. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
:class: width-helper
:class: width-helper invert-helper

4
docs/source/using_yosys/synthesis/memory.rst
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@ -39,7 +39,7 @@ Example
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
.. figure:: /_images/code_examples/synth_flow/memory_01.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/synth_flow/memory_01.ys
:language: yoscrypt
@ -50,7 +50,7 @@ Example
:caption: :file:`memory_01.v`
.. figure:: /_images/code_examples/synth_flow/memory_02.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/synth_flow/memory_02.v
:language: verilog

8
docs/source/using_yosys/synthesis/opt.rst
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@ -88,7 +88,7 @@ trees can interfere with other optimizations.
:caption: example verilog for demonstrating :cmd:ref:`opt_expr`
.. figure:: /_images/code_examples/opt/opt_expr.*
:class: width-helper
:class: width-helper invert-helper
Before and after :cmd:ref:`opt_expr`
@ -111,7 +111,7 @@ possible optimizations.
:caption: example verilog for demonstrating :cmd:ref:`opt_merge`
.. figure:: /_images/code_examples/opt/opt_merge.*
:class: width-helper
:class: width-helper invert-helper
Before and after :cmd:ref:`opt_merge`
@ -133,7 +133,7 @@ detects this contradiction and replaces the inner multiplexer with a constant 1,
yielding the logic for ``y = a ? b : d``.
.. figure:: /_images/code_examples/opt/opt_muxtree.*
:class: width-helper
:class: width-helper invert-helper
Before and after :cmd:ref:`opt_muxtree`
@ -172,7 +172,7 @@ multiplexing its output to multiplexing the non-shared input signals.
:caption: example verilog for demonstrating :cmd:ref:`opt_share`
.. figure:: /_images/code_examples/opt/opt_share.*
:class: width-helper
:class: width-helper invert-helper
Before and after :cmd:ref:`opt_share`

6
docs/source/using_yosys/synthesis/proc.rst
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@ -42,10 +42,10 @@ Example
:caption: :file:`proc_01.ys`
.. figure:: /_images/code_examples/synth_flow/proc_01.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/synth_flow/proc_02.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/synth_flow/proc_02.v
:language: verilog
@ -56,7 +56,7 @@ Example
:caption: :file:`proc_02.ys`
.. figure:: /_images/code_examples/synth_flow/proc_03.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/synth_flow/proc_03.ys
:language: yoscrypt