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Docs: Apply invert-helper where needed

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Krystine Sherwin 2024-05-11 10:40:54 +12:00
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24
docs/source/using_yosys/more_scripting/interactive_investigation.rst
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@ -56,7 +56,7 @@ is shown.
``xdot example_first.dot`` etc.
.. figure:: /_images/code_examples/show/example_first.*
:class: width-helper
:class: width-helper invert-helper
Output of the first :cmd:ref:`show` command in :numref:`example_ys`
@ -88,7 +88,7 @@ The :cmd:ref:`proc` command transforms the process from the first diagram into a
multiplexer and a d-type flip-flop, which brings us to the second diagram:
.. figure:: /_images/code_examples/show/example_second.*
:class: width-helper
:class: width-helper invert-helper
Output of the second :cmd:ref:`show` command in :numref:`example_ys`
@ -110,7 +110,7 @@ In this script we directly call :cmd:ref:`opt` as the next step, which finally
leads us to the third diagram:
.. figure:: /_images/code_examples/show/example_third.*
:class: width-helper
:class: width-helper invert-helper
:name: example_out
Output of the third :cmd:ref:`show` command in :ref:`example_ys`
@ -137,7 +137,7 @@ that operate on wide integers, it also introduces some additional complexity
when the individual bits of of a signal vector are accessed.
.. figure:: /_images/code_examples/show/splice.*
:class: width-helper
:class: width-helper invert-helper
:name: splice_dia
Output of ``yosys -p 'prep -top splice_demo; show' splice.v``
@ -165,7 +165,7 @@ Gate level netlists
mapped to a cell library:
.. figure:: /_images/code_examples/show/cmos_00.*
:class: width-helper
:class: width-helper invert-helper
:name: first_pitfall
A half-adder built from simple CMOS gates, demonstrating common pitfalls when
@ -185,7 +185,7 @@ column. Secondly the two-bit vector ``y`` requires breakout-boxes for its
individual bits, resulting in an unnecessary complex diagram.
.. figure:: /_images/code_examples/show/cmos_01.*
:class: width-helper
:class: width-helper invert-helper
:name: second_pitfall
Effects of :cmd:ref:`splitnets` command and of providing a cell library on
@ -358,10 +358,10 @@ reorganizing a module in Yosys and checking the resulting circuit.
:end-before: cd ..
.. figure:: /_images/code_examples/scrambler/scrambler_p01.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/scrambler/scrambler_p02.*
:class: width-helper
:class: width-helper invert-helper
Analyzing the resulting circuit with :doc:`/cmd/eval`:
@ -442,7 +442,7 @@ if the circuit under investigation is encapsulated in a separate module.
Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
.. figure:: /_images/code_examples/selections/memdemo_00.*
:class: width-helper
:class: width-helper invert-helper
``memdemo``
@ -463,18 +463,18 @@ name of the new cell in the current module. The resulting circuits are shown
below.
.. figure:: /_images/code_examples/selections/submod_02.*
:class: width-helper
:class: width-helper invert-helper
``outstage``
.. figure:: /_images/code_examples/selections/submod_03.*
:class: width-helper
:class: width-helper invert-helper
:name: selstage
``selstage``
.. figure:: /_images/code_examples/selections/submod_01.*
:class: width-helper
:class: width-helper invert-helper
``scramble``

26
docs/source/using_yosys/more_scripting/selections.rst
View file

@ -160,7 +160,7 @@ Selecting ``a:sumstuff`` in this module will yield the following circuit
diagram:
.. figure:: /_images/code_examples/selections/sumprod_00.*
:class: width-helper
:class: width-helper invert-helper
:name: sumprod_00
Output of ``show a:sumstuff`` on :numref:`sumprod`
@ -177,7 +177,7 @@ selected wire it selects all cells connected to the wire and vice versa. So
:yoscrypt:`show a:sumstuff %x` yields the diagram shown in :numref:`sumprod_01`:
.. figure:: /_images/code_examples/selections/sumprod_01.*
:class: width-helper
:class: width-helper invert-helper
:name: sumprod_01
Output of ``show a:sumstuff %x`` on :numref:`sumprod`
@ -200,22 +200,22 @@ input ports.
The following sequence of diagrams demonstrates this step-wise expansion:
.. figure:: /_images/code_examples/selections/sumprod_02.*
:class: width-helper
:class: width-helper invert-helper
Output of :yoscrypt:`show prod` on :numref:`sumprod`
.. figure:: /_images/code_examples/selections/sumprod_03.*
:class: width-helper
:class: width-helper invert-helper
Output of :yoscrypt:`show prod %ci` on :numref:`sumprod`
.. figure:: /_images/code_examples/selections/sumprod_04.*
:class: width-helper
:class: width-helper invert-helper
Output of :yoscrypt:`show prod %ci %ci` on :numref:`sumprod`
.. figure:: /_images/code_examples/selections/sumprod_05.*
:class: width-helper
:class: width-helper invert-helper
Output of :yoscrypt:`show prod %ci %ci %ci` on :numref:`sumprod`
@ -280,7 +280,7 @@ provided :file:`memdemo.v` is in the same directory. We can now change to the
diagram in :numref:`memdemo_00`.
.. figure:: /_images/code_examples/selections/memdemo_00.*
:class: width-helper
:class: width-helper invert-helper
:name: memdemo_00
Complete circuit diagram for the design shown in :numref:`memdemo_src`
@ -291,7 +291,7 @@ output signal, ``y``, and its immediate predecessors. Remember `Selecting logic
cones`_ from above, we can use :yoscrypt:`show y %ci2`:
.. figure:: /_images/code_examples/selections/memdemo_01.*
:class: width-helper
:class: width-helper invert-helper
:name: memdemo_01
Output of :yoscrypt:`show y %ci2`
@ -303,7 +303,7 @@ wire into the input ``D`` of the flip-flop cell (indicated by the ``$`` at the
start of the name). Let's go a bit further now and try :yoscrypt:`show y %ci5`:
.. figure:: /_images/code_examples/selections/memdemo_02.*
:class: width-helper
:class: width-helper invert-helper
:name: memdemo_02
Output of :yoscrypt:`show y %ci5`
@ -317,7 +317,7 @@ brackets. In this case, we want to exclude the ``S`` port of the ``$mux`` cell
type with :yoscrypt:`show y %ci5:-$mux[S]`:
.. figure:: /_images/code_examples/selections/memdemo_03.*
:class: width-helper
:class: width-helper invert-helper
:name: memdemo_03
Output of :yoscrypt:`show y %ci5:-$mux[S]`
@ -328,7 +328,7 @@ flip-flop and the 2nd action selects the entire input cone without going over
multiplexer select inputs and flip-flop cells:
.. figure:: /_images/code_examples/selections/memdemo_05.*
:class: width-helper
:class: width-helper invert-helper
:name: memdemo_05
Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``
@ -340,7 +340,7 @@ ignoring any ports named ``CLK`` or ``S``:
.. TODO:: pending discussion on whether rule ordering is a bug or a feature
.. figure:: /_images/code_examples/selections/memdemo_04.*
:class: width-helper
:class: width-helper invert-helper
:name: memdemo_04
Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux`
@ -417,6 +417,6 @@ Example code from |code_examples/selections|_:
:name: select_ys
.. figure:: /_images/code_examples/selections/select.*
:class: width-helper
:class: width-helper invert-helper
Circuit diagram produced by :numref:`select_ys`

8
docs/source/using_yosys/synthesis/cell_libs.rst
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@ -51,7 +51,7 @@ Loading the design
Our circuit now looks like this:
.. figure:: /_images/code_examples/intro/counter_00.*
:class: width-helper
:class: width-helper invert-helper
:name: counter-hierarchy
``counter`` after :cmd:ref:`hierarchy`
@ -66,7 +66,7 @@ Coarse-grain representation
:caption: :file:`counter.ys` - the high-level stuff
.. figure:: /_images/code_examples/intro/counter_01.*
:class: width-helper
:class: width-helper invert-helper
Coarse-grain representation of the ``counter`` module
@ -80,7 +80,7 @@ Logic gate mapping
:caption: :file:`counter.ys` - mapping to internal cell library
.. figure:: /_images/code_examples/intro/counter_02.*
:class: width-helper
:class: width-helper invert-helper
``counter`` after :cmd:ref:`techmap`
@ -111,7 +111,7 @@ Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
The final version of our ``counter`` module looks like this:
.. figure:: /_images/code_examples/intro/counter_03.*
:class: width-helper
:class: width-helper invert-helper
``counter`` after hardware cell mapping

40
docs/source/using_yosys/synthesis/extract.rst
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@ -23,7 +23,7 @@ Example code can be found in |code_examples/macc|_.
:lines: 1-2
.. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
:class: width-helper
:class: width-helper invert-helper
before :cmd:ref:`extract`
@ -32,7 +32,7 @@ Example code can be found in |code_examples/macc|_.
:lines: 6
.. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
:class: width-helper
:class: width-helper invert-helper
after :cmd:ref:`extract`
@ -49,20 +49,20 @@ Example code can be found in |code_examples/macc|_.
:caption: :file:`macc_simple_test_01.v`
.. figure:: /_images/code_examples/macc/macc_simple_test_01a.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/macc/macc_simple_test_01b.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_simple_test_02.v
:language: verilog
:caption: :file:`macc_simple_test_02.v`
.. figure:: /_images/code_examples/macc/macc_simple_test_02a.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/macc/macc_simple_test_02b.*
:class: width-helper
:class: width-helper invert-helper
The wrap-extract-unwrap method
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -149,10 +149,10 @@ Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
:caption: ``test1`` of :file:`macc_xilinx_test.v`
.. figure:: /_images/code_examples/macc/macc_xilinx_test1a.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
:language: verilog
@ -160,15 +160,15 @@ Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
:caption: ``test2`` of :file:`macc_xilinx_test.v`
.. figure:: /_images/code_examples/macc/macc_xilinx_test2a.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
:class: width-helper
:class: width-helper invert-helper
Wrapping in ``test1``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -176,12 +176,12 @@ Wrapping in ``test1``:
:end-before: end part c
.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
:class: width-helper
:class: width-helper invert-helper
Wrapping in ``test2``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -189,12 +189,12 @@ Wrapping in ``test2``:
:end-before: end part c
.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
:class: width-helper
:class: width-helper invert-helper
Extract in ``test1``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -202,12 +202,12 @@ Extract in ``test1``:
:end-before: end part d
.. figure:: /_images/code_examples/macc/macc_xilinx_test1d.*
:class: width-helper
:class: width-helper invert-helper
Extract in ``test2``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -215,12 +215,12 @@ Extract in ``test2``:
:end-before: end part d
.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
:class: width-helper
:class: width-helper invert-helper
Unwrap in ``test2``:
.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
:language: yoscrypt
@ -228,4 +228,4 @@ Unwrap in ``test2``:
:end-before: end part e
.. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
:class: width-helper
:class: width-helper invert-helper

4
docs/source/using_yosys/synthesis/memory.rst
View file

@ -39,7 +39,7 @@ Example
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
.. figure:: /_images/code_examples/synth_flow/memory_01.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/synth_flow/memory_01.ys
:language: yoscrypt
@ -50,7 +50,7 @@ Example
:caption: :file:`memory_01.v`
.. figure:: /_images/code_examples/synth_flow/memory_02.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/synth_flow/memory_02.v
:language: verilog

8
docs/source/using_yosys/synthesis/opt.rst
View file

@ -88,7 +88,7 @@ trees can interfere with other optimizations.
:caption: example verilog for demonstrating :cmd:ref:`opt_expr`
.. figure:: /_images/code_examples/opt/opt_expr.*
:class: width-helper
:class: width-helper invert-helper
Before and after :cmd:ref:`opt_expr`
@ -111,7 +111,7 @@ possible optimizations.
:caption: example verilog for demonstrating :cmd:ref:`opt_merge`
.. figure:: /_images/code_examples/opt/opt_merge.*
:class: width-helper
:class: width-helper invert-helper
Before and after :cmd:ref:`opt_merge`
@ -133,7 +133,7 @@ detects this contradiction and replaces the inner multiplexer with a constant 1,
yielding the logic for ``y = a ? b : d``.
.. figure:: /_images/code_examples/opt/opt_muxtree.*
:class: width-helper
:class: width-helper invert-helper
Before and after :cmd:ref:`opt_muxtree`
@ -172,7 +172,7 @@ multiplexing its output to multiplexing the non-shared input signals.
:caption: example verilog for demonstrating :cmd:ref:`opt_share`
.. figure:: /_images/code_examples/opt/opt_share.*
:class: width-helper
:class: width-helper invert-helper
Before and after :cmd:ref:`opt_share`

6
docs/source/using_yosys/synthesis/proc.rst
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@ -42,10 +42,10 @@ Example
:caption: :file:`proc_01.ys`
.. figure:: /_images/code_examples/synth_flow/proc_01.*
:class: width-helper
:class: width-helper invert-helper
.. figure:: /_images/code_examples/synth_flow/proc_02.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/synth_flow/proc_02.v
:language: verilog
@ -56,7 +56,7 @@ Example
:caption: :file:`proc_02.ys`
.. figure:: /_images/code_examples/synth_flow/proc_03.*
:class: width-helper
:class: width-helper invert-helper
.. literalinclude:: /code_examples/synth_flow/proc_03.ys
:language: yoscrypt