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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-05-24 12:11:52 -07:00 • committed by GitHub
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12 changed files with 87 additions and 9 deletions
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12
tests/liberty/libcache.ys
View file

@ -1,3 +1,4 @@
libcache -verbose
libcache -enable busdef.lib
logger -expect log "Caching is disabled by default." 1
@ -14,8 +15,8 @@ logger -expect log "Caching data" 1
read_liberty -lib busdef.lib; design -reset
logger -check-expected
logger -expect log "Using caching data" 1
log Using caching data
logger -expect log "Using cached data" 1
log Using cached data
read_liberty normal.lib; design -reset
logger -check-expected
@ -23,6 +24,13 @@ logger -expect log "Using cached data" 1
read_liberty -lib busdef.lib; design -reset
logger -check-expected
libcache -quiet
logger -expect log "Using cached data" 1
log Using cached data
read_liberty -lib busdef.lib; design -reset
logger -check-expected
libcache -verbose
libcache -purge busdef.lib
logger -expect log "Caching is disabled by default." 1

30
tests/verilog/sbvector.ys Normal file
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@ -0,0 +1,30 @@
read_verilog <<EOT
module foo(
output o,
input [0:0] i1,
input i2
);
wire [0:0] w1 = i1 ^ i2;
wire w2 = ~i1;
assign o = w1 ^ w2;
endmodule
EOT
hierarchy
proc
select -assert-count 1 w:i1
select -assert-count 1 w:i1 a:single_bit_vector %i
select -assert-count 1 w:i2
select -assert-count 0 w:i2 a:single_bit_vector %i
select -assert-count 1 w:w1
select -assert-count 1 w:w1 a:single_bit_vector %i
select -assert-count 1 w:w2
select -assert-count 0 w:w2 a:single_bit_vector %i
write_verilog verilog_sbvector.out
!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
!grep -qF 'input [0:0] i1;' verilog_sbvector.out
!grep -qF 'wire i2;' verilog_sbvector.out
!grep -qF 'input i2;' verilog_sbvector.out
!grep -qF 'wire [0:0] w1;' verilog_sbvector.out
!grep -qF 'wire w2;' verilog_sbvector.out