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celledges: Describe asynchronous read ports
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@ -307,6 +307,40 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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}
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}
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}
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}
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void packed_mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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log_assert(cell->type == ID($mem_v2));
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Const rd_clk_enable = cell->getParam(ID::RD_CLK_ENABLE);
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int n_rd_ports = cell->getParam(ID::RD_PORTS).as_int();
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int abits = cell->getParam(ID::ABITS).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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for (int i = 0; i < n_rd_ports; i++) {
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if (rd_clk_enable[i] != State::S0)
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continue;
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for (int j = 0; j < abits; j++)
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::RD_ADDR, i * abits + j,
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ID::RD_DATA, i * width + k, -1);
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}
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}
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void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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log_assert(cell->type.in(ID($memrd), ID($memrd_v2)));
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if (cell->getParam(ID::CLK_ENABLE).as_bool())
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return;
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int abits = cell->getParam(ID::ABITS).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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for (int j = 0; j < abits; j++)
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ADDR, j, ID::DATA, k, -1);
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}
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PRIVATE_NAMESPACE_END
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PRIVATE_NAMESPACE_END
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bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
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bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
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@ -361,6 +395,16 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
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return true;
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return true;
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}
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}
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if (cell->type == ID($mem_v2)) {
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packed_mem_op(this, cell);
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return true;
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}
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if (cell->type.in(ID($memrd), ID($memrd_v2))) {
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memrd_op(this, cell);
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return true;
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}
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// FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx
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// FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx
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// FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux
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// FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux
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