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Add cell_libs.rst

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Updates code examples, removing `counter_outputs.ys` in favour of a single script.  Also adds a .gitignore for the output file `synth.v`.
`example_synth.rst` still pending updated example.
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Krystine Sherwin 2023-12-14 10:08:46 +13:00
parent f44e8d0124
commit 3a153f99db
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docs/source/using_yosys/synthesis/index.rst
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@ -12,4 +12,5 @@ Synthesis in detail
memory
opt
abc
cell_libs