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Add cell_libs.rst

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Updates code examples, removing `counter_outputs.ys` in favour of a single script.  Also adds a .gitignore for the output file `synth.v`.
`example_synth.rst` still pending updated example.
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Krystine Sherwin 2023-12-14 10:08:46 +13:00
parent f44e8d0124
commit 3a153f99db
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6 changed files with 145 additions and 32 deletions
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12
docs/source/code_examples/intro/counter.ys
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@ -2,12 +2,20 @@
read_verilog counter.v
hierarchy -check -top counter
show -notitle -format dot -prefix counter_00
# the high-level stuff
proc; opt; memory; opt; fsm; opt
proc; opt
memory; opt
fsm; opt
show -notitle -format dot -prefix counter_01
# mapping to internal cell library
techmap; opt
splitnets -ports;; show -notitle -format dot -prefix counter_02
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
@ -17,5 +25,7 @@ abc -liberty mycells.lib
# cleanup
clean
show -notitle -lib mycells.v -format dot -prefix counter_03
# write synthesized design
write_verilog synth.v