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Add cell_libs.rst
Updates code examples, removing `counter_outputs.ys` in favour of a single script. Also adds a .gitignore for the output file `synth.v`. `example_synth.rst` still pending updated example.
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6 changed files with 145 additions and 32 deletions
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docs/source/code_examples/intro/.gitignore
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docs/source/code_examples/intro/.gitignore
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@ -0,0 +1 @@
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synth.v
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@ -2,12 +2,12 @@ PROGRAM_PREFIX :=
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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DOTS = counter_00.dot counter_proc.dot counter_01.dot counter_02.dot counter_03.dot
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DOTS = counter_00.dot counter_01.dot counter_02.dot counter_03.dot
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dots: $(DOTS)
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$(DOTS): counter.v counter_outputs.ys mycells.lib
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$(YOSYS) counter_outputs.ys
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$(DOTS): counter.v counter.ys mycells.lib
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$(YOSYS) counter.ys
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.PHONY: clean
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clean:
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@ -2,12 +2,20 @@
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read_verilog counter.v
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hierarchy -check -top counter
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show -notitle -format dot -prefix counter_00
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# the high-level stuff
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proc; opt; memory; opt; fsm; opt
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proc; opt
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memory; opt
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fsm; opt
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show -notitle -format dot -prefix counter_01
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# mapping to internal cell library
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techmap; opt
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splitnets -ports;; show -notitle -format dot -prefix counter_02
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# mapping flip-flops to mycells.lib
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dfflibmap -liberty mycells.lib
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@ -17,5 +25,7 @@ abc -liberty mycells.lib
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# cleanup
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clean
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show -notitle -lib mycells.v -format dot -prefix counter_03
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# write synthesized design
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write_verilog synth.v
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@ -1,28 +0,0 @@
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# read
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read_verilog counter.v
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hierarchy -check -top counter
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show -notitle -format dot -prefix counter_00
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# elaborate
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proc
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show -notitle -format dot -prefix counter_proc
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opt
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show -notitle -format dot -prefix counter_01
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# mapping to internal cell library
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techmap; opt
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splitnets -ports;;
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show -notitle -format dot -prefix counter_02
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# mapping flip-flops to mycells.lib
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dfflibmap -liberty mycells.lib
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# mapping logic to mycells.lib
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abc -liberty mycells.lib
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# cleanup
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clean
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show -notitle -lib mycells.v -format dot -prefix counter_03
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