mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-18 06:39:03 +00:00
tests: Update path to sim model
This commit is contained in:
parent
b6a9d78507
commit
397f748dd2
|
@ -1,4 +1,4 @@
|
|||
verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
|
||||
verific -sv -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
|
||||
|
||||
verific -sv <<EOF
|
||||
module top (
|
||||
|
|
Loading…
Reference in a new issue