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Support for SystemVerilog interfaces as a port in the top level module + test case

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This commit is contained in:
Ruben Undheim 2018-10-20 11:58:25 +02:00
parent d9a4381012
commit 397dfccb30
9 changed files with 561 additions and 10 deletions
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7
tests/svinterfaces/runone.sh
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@ -22,11 +22,14 @@ iverilog -g2012 ${TESTNAME}_syn.v
iverilog -g2012 ${TESTNAME}_ref_syn.v
set +e
iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
./a.out
mv output.txt reference_result.txt
iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
if [ -f ${TESTNAME}_wrapper.v ] ; then
iverilog -g2012 ${TESTNAME}_tb_wrapper.v ${TESTNAME}_syn.v
else
iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
fi
./a.out
mv output.txt dut_result.txt