mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-17 08:42:16 +00:00
Support for SystemVerilog interfaces as a port in the top level module + test case
This commit is contained in:
Ruben Undheim
parent
d9a4381012
commit
397dfccb30
9 changed files with 561 additions and 10 deletions
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@ -3,3 +3,4 @@
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./runone.sh svinterface1
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./runone.sh svinterface_at_top
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@ -22,11 +22,14 @@ iverilog -g2012 ${TESTNAME}_syn.v
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iverilog -g2012 ${TESTNAME}_ref_syn.v
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set +e
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iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
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./a.out
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mv output.txt reference_result.txt
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iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
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if [ -f ${TESTNAME}_wrapper.v ] ; then
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iverilog -g2012 ${TESTNAME}_tb_wrapper.v ${TESTNAME}_syn.v
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else
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iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
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fi
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./a.out
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mv output.txt dut_result.txt
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125
tests/svinterfaces/svinterface_at_top.sv
Normal file
125
tests/svinterfaces/svinterface_at_top.sv
Normal file
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@ -0,0 +1,125 @@
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module TopModule(
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input logic clk,
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input logic rst,
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output logic [21:0] outOther,
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input logic [1:0] sig,
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input logic flip,
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output logic [1:0] sig_out,
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MyInterface.submodule1 interfaceInstanceAtTop,
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output logic [15:0] passThrough);
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MyInterface #(.WIDTH(4)) MyInterfaceInstance();
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SubModule1 u_SubModule1 (
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.clk(clk),
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.rst(rst),
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.u_MyInterface(MyInterfaceInstance),
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.u_MyInterfaceFromTop(interfaceInstanceAtTop),
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.outOther(outOther),
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.sig (sig)
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);
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assign sig_out = MyInterfaceInstance.mysig_out;
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assign MyInterfaceInstance.setting = flip;
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assign passThrough = MyInterfaceInstance.passThrough;
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endmodule
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interface MyInterface #(
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parameter WIDTH = 3)(
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);
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logic setting;
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logic [WIDTH-1:0] other_setting;
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logic [1:0] mysig_out;
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logic [15:0] passThrough;
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modport submodule1 (
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input setting,
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output other_setting,
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output mysig_out,
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output passThrough
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);
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modport submodule2 (
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input setting,
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output other_setting,
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input mysig_out,
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output passThrough
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);
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endinterface
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module SubModule1(
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input logic clk,
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input logic rst,
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MyInterface.submodule1 u_MyInterface,
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MyInterface.submodule1 u_MyInterfaceFromTop,
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input logic [1:0] sig,
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output logic [21:0] outOther
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);
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always_ff @(posedge clk or posedge rst)
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if(rst)
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u_MyInterface.mysig_out <= 0;
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else begin
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if(u_MyInterface.setting)
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u_MyInterface.mysig_out <= sig;
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else
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u_MyInterface.mysig_out <= ~sig;
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end
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MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
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SubModule2 u_SubModule2 (
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.clk(clk),
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.rst(rst),
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.u_MyInterfaceFromTopDown(u_MyInterfaceFromTop),
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.u_MyInterfaceInSub2(u_MyInterface),
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.u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
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);
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assign outOther = MyInterfaceInstanceInSub.other_setting;
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assign MyInterfaceInstanceInSub.setting = 0;
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assign MyInterfaceInstanceInSub.mysig_out = sig;
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endmodule
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module SubModule2(
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input logic clk,
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input logic rst,
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MyInterface.submodule2 u_MyInterfaceInSub2,
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MyInterface.submodule1 u_MyInterfaceFromTopDown,
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MyInterface.submodule2 u_MyInterfaceInSub3
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);
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assign u_MyInterfaceFromTopDown.mysig_out = u_MyInterfaceFromTop.setting ? 10 : 20;
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always_comb begin
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if (u_MyInterfaceInSub3.mysig_out == 2'b00)
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u_MyInterfaceInSub3.other_setting[21:0] = 1000;
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else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
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u_MyInterfaceInSub3.other_setting[21:0] = 2000;
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else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
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u_MyInterfaceInSub3.other_setting[21:0] = 3000;
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else
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u_MyInterfaceInSub3.other_setting[21:0] = 4000;
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end
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assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
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assign u_MyInterfaceInSub2.passThrough[15:8] = 200;
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endmodule
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120
tests/svinterfaces/svinterface_at_top_ref.v
Normal file
120
tests/svinterfaces/svinterface_at_top_ref.v
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@ -0,0 +1,120 @@
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module TopModule(
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input logic clk,
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input logic rst,
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input logic [1:0] sig,
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input logic flip,
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output logic [15:0] passThrough,
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output logic [21:0] outOther,
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input logic interfaceInstanceAtTop_setting,
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output logic [2:0] interfaceInstanceAtTop_other_setting,
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output logic [1:0] interfaceInstanceAtTop_mysig_out,
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output logic [15:0] interfaceInstanceAtTop_passThrough,
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output logic [1:0] sig_out);
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logic MyInterfaceInstance_setting;
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logic [3:0] MyInterfaceInstance_other_setting;
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logic [1:0] MyInterfaceInstance_mysig_out;
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SubModule1 u_SubModule1 (
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.clk(clk),
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.rst(rst),
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.u_MyInterface_setting(MyInterfaceInstance_setting),
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.u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
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.u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
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.u_MyInterfaceFromTop_setting(interfaceInstanceAtTop_setting),
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.u_MyInterfaceFromTop_other_setting(interfaceInstanceAtTop_other_setting),
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.u_MyInterfaceFromTop_mysig_out(interfaceInstanceAtTop_mysig_out),
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.u_MyInterfaceFromTop_passThrough(interfaceInstanceAtTop_passThrough),
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.outOther(outOther),
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.passThrough (passThrough),
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.sig (sig)
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);
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assign sig_out = MyInterfaceInstance_mysig_out;
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assign MyInterfaceInstance_setting = flip;
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endmodule
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module SubModule1(
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input logic clk,
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input logic rst,
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input logic u_MyInterface_setting,
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output logic [3:0] u_MyInterface_other_setting,
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output logic [1:0] u_MyInterface_mysig_out,
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output logic [21:0] outOther,
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input logic [1:0] sig,
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input logic u_MyInterfaceFromTop_setting,
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output logic [2:0] u_MyInterfaceFromTop_other_setting,
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output logic [1:0] u_MyInterfaceFromTop_mysig_out,
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output logic [14:0] u_MyInterfaceFromTop_passThrough,
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output logic [15:0] passThrough
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);
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always @(posedge clk or posedge rst)
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if(rst)
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u_MyInterface_mysig_out <= 0;
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else begin
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if(u_MyInterface_setting)
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u_MyInterface_mysig_out <= sig;
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else
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u_MyInterface_mysig_out <= ~sig;
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end
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logic MyInterfaceInstanceInSub_setting;
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logic [21:0] MyInterfaceInstanceInSub_other_setting;
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logic [1:0] MyInterfaceInstanceInSub_mysig_out;
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assign u_MyInterfaceFromTop_mysig_out = u_MyInterfaceFromTop_setting ? 10 : 20;
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SubModule2 u_SubModule2 (
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.clk(clk),
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.rst(rst),
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.u_MyInterfaceInSub2_setting(u_MyInterface_setting),
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.u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
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.u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
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.u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
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.u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
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.u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
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.passThrough (passThrough)
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);
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assign outOther = MyInterfaceInstanceInSub_other_setting;
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assign MyInterfaceInstanceInSub_setting = 0;
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assign MyInterfaceInstanceInSub_mysig_out = sig;
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endmodule
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module SubModule2(
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input logic clk,
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input logic rst,
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input logic u_MyInterfaceInSub2_setting,
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output logic [3:0] u_MyInterfaceInSub2_other_setting,
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input logic [1:0] u_MyInterfaceInSub2_mysig_out,
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input logic u_MyInterfaceInSub3_setting,
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output logic [21:0] u_MyInterfaceInSub3_other_setting,
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input logic [1:0] u_MyInterfaceInSub3_mysig_out,
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output logic [15:0] passThrough
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);
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always @(u_MyInterfaceInSub3_mysig_out) begin
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if (u_MyInterfaceInSub3_mysig_out == 2'b00)
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u_MyInterfaceInSub3_other_setting[21:0] = 1000;
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else if (u_MyInterfaceInSub3_mysig_out == 2'b01)
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u_MyInterfaceInSub3_other_setting[21:0] = 2000;
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else if (u_MyInterfaceInSub3_mysig_out == 2'b10)
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u_MyInterfaceInSub3_other_setting[21:0] = 3000;
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else
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u_MyInterfaceInSub3_other_setting[21:0] = 4000;
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end
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assign passThrough[7:0] = 124;
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assign passThrough[15:8] = 200;
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endmodule
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68
tests/svinterfaces/svinterface_at_top_tb.v
Normal file
68
tests/svinterfaces/svinterface_at_top_tb.v
Normal file
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@ -0,0 +1,68 @@
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`timescale 1ns/10ps
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module svinterface_at_top_tb;
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logic clk;
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logic rst;
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logic [21:0] outOther;
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logic [1:0] sig;
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logic [1:0] sig_out;
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logic flip;
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logic [15:0] passThrough;
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integer outfile;
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logic interfaceInstanceAtTop_setting;
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logic [2:0] interfaceInstanceAtTop_other_setting;
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logic [1:0] interfaceInstanceAtTop_mysig_out;
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logic [15:0] interfaceInstanceAtTop_passThrough;
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TopModule u_dut (
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.clk(clk),
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.rst(rst),
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.outOther(outOther),
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.sig(sig),
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.flip(flip),
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.passThrough(passThrough),
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.interfaceInstanceAtTop_setting(interfaceInstanceAtTop_setting),
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.interfaceInstanceAtTop_other_setting(interfaceInstanceAtTop_other_setting),
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.interfaceInstanceAtTop_mysig_out(interfaceInstanceAtTop_mysig_out),
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.interfaceInstanceAtTop_passThrough(interfaceInstanceAtTop_passThrough),
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.sig_out(sig_out)
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);
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initial begin
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clk = 0;
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while(1) begin
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clk = ~clk;
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#50;
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end
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end
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initial begin
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outfile = $fopen("output.txt");
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rst = 1;
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interfaceInstanceAtTop_setting = 0;
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sig = 0;
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flip = 0;
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@(posedge clk);
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#(2);
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rst = 0;
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@(posedge clk);
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for(int j=0;j<2;j++) begin
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for(int i=0;i<20;i++) begin
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#(2);
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flip = j;
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sig = i;
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@(posedge clk);
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end
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end
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$finish;
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end
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always @(negedge clk) begin
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$fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
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end
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endmodule
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68
tests/svinterfaces/svinterface_at_top_tb_wrapper.v
Normal file
68
tests/svinterfaces/svinterface_at_top_tb_wrapper.v
Normal file
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@ -0,0 +1,68 @@
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`timescale 1ns/10ps
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module svinterface_at_top_tb_wrapper;
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logic clk;
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logic rst;
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logic [21:0] outOther;
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logic [1:0] sig;
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logic [1:0] sig_out;
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logic flip;
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logic [15:0] passThrough;
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integer outfile;
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logic interfaceInstanceAtTop_setting;
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logic [2:0] interfaceInstanceAtTop_other_setting;
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logic [1:0] interfaceInstanceAtTop_mysig_out;
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logic [15:0] interfaceInstanceAtTop_passThrough;
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TopModule u_dut (
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.clk(clk),
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.rst(rst),
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.outOther(outOther),
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.sig(sig),
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.flip(flip),
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.passThrough(passThrough),
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.\interfaceInstanceAtTop.setting (interfaceInstanceAtTop_setting),
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.\interfaceInstanceAtTop.other_setting (interfaceInstanceAtTop_other_setting),
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.\interfaceInstanceAtTop.mysig_out (interfaceInstanceAtTop_mysig_out),
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.\interfaceInstanceAtTop.passThrough (interfaceInstanceAtTop_passThrough),
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.sig_out(sig_out)
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);
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initial begin
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clk = 0;
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while(1) begin
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clk = ~clk;
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#50;
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end
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end
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initial begin
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outfile = $fopen("output.txt");
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rst = 1;
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sig = 0;
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interfaceInstanceAtTop_setting = 0;
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flip = 0;
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@(posedge clk);
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#(2);
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rst = 0;
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@(posedge clk);
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for(int j=0;j<2;j++) begin
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for(int i=0;i<20;i++) begin
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#(2);
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flip = j;
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sig = i;
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@(posedge clk);
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end
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end
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$finish;
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end
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always @(negedge clk) begin
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$fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
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end
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endmodule
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33
tests/svinterfaces/svinterface_at_top_wrapper.v
Normal file
33
tests/svinterfaces/svinterface_at_top_wrapper.v
Normal file
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@ -0,0 +1,33 @@
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`timescale 1ns/10ps
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module svinterface_at_top_wrapper(
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input logic clk,
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input logic rst,
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output logic [21:0] outOther,
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input logic [1:0] sig,
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output logic [1:0] sig_out,
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input logic flip,
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output logic [15:0] passThrough,
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input logic interfaceInstanceAtTop_setting,
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output logic [2:0] interfaceInstanceAtTop_other_setting,
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output logic [1:0] interfaceInstanceAtTop_mysig_out,
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output logic [15:0] interfaceInstanceAtTop_passThrough,
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);
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TopModule u_dut (
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.clk(clk),
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.rst(rst),
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.outOther(outOther),
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.sig(sig),
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.flip(flip),
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.passThrough(passThrough),
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.\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting),
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.\interfaceInstanceAtTop.other_setting(interfaceInstanceAtTop_other_setting),
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.\interfaceInstanceAtTop.mysig_out(interfaceInstanceAtTop_mysig_out),
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.\interfaceInstanceAtTop.passThrough(interfaceInstanceAtTop_passThrough),
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.sig_out(sig_out)
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);
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endmodule
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