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Reapply "Add groups to command reference"

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This reverts commit 81f87ce6ed.
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Krystine Sherwin 2025-08-06 13:52:12 +12:00
parent 2ad3532a55
commit 3959d19291
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docs/source/using_yosys/verilog.rst
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@ -94,7 +94,7 @@ Verilog Attributes and non-standard features
- The ``keep_hierarchy`` attribute on cells and modules keeps the `flatten`
command from flattening the indicated cells and modules.
- The `gate_cost_equivalent` attribute on a module can be used to specify
- The ``gate_cost_equivalent`` attribute on a module can be used to specify
the estimated cost of the module as a number of basic gate instances. See
the help message of command `keep_hierarchy` which interprets this
attribute.