mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-30 21:57:47 +00:00
Code Activity

docs: document S&R undefined for $dffsr and $dffsre

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-03-04 19:39:41 +01:00
parent 126492742b
commit 39343f5f33
2 changed files with 9 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
docs/source/cell/word_reg.rst
View file

@ -78,6 +78,7 @@ D-type flip-flops with asynchronous set and reset are represented by `$dffsr`
cells. As the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition
they also have multi-bit ``SET`` and ``CLR`` input ports and the corresponding
polarity parameters, like `$sr` cells.
When both set and reset are active, the state and output is undefined.
D-type flip-flops with enable are represented by `$dffe`, `$adffe`, `$aldffe`,
`$dffsre`, `$sdffe`, and `$sdffce` cells, which are enhanced variants of `$dff`,