diff --git a/docs/source/cell/gate_reg_ff.rst b/docs/source/cell/gate_reg_ff.rst
index 2a31a3f09..2689c9def 100644
--- a/docs/source/cell/gate_reg_ff.rst
+++ b/docs/source/cell/gate_reg_ff.rst
@@ -154,6 +154,10 @@ to the following Verilog code template, where ``RST_EDGE`` is ``posedge`` if
 ``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is ``posedge`` if
 ``SET_LVL`` if ``1``, ``negedge`` otherwise.
 
+When both set and reset are active, the state and output is undefined. The Verilog
+code model does not correspond to this due to limitations
+of synthesizable Verilog.
+
 .. code-block:: verilog
    :force:
 
@@ -187,6 +191,10 @@ types relate to the following Verilog code template, where ``RST_EDGE`` is
 ``posedge`` if ``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is
 ``posedge`` if ``SET_LVL`` if ``1``, ``negedge`` otherwise.
 
+When both set and reset are active, the state and output is undefined. The Verilog
+code model does not correspond to this due to limitations
+of synthesizable Verilog.
+
 .. code-block:: verilog
    :force:
 
diff --git a/docs/source/cell/word_reg.rst b/docs/source/cell/word_reg.rst
index 25c82b8e6..c5b369b33 100644
--- a/docs/source/cell/word_reg.rst
+++ b/docs/source/cell/word_reg.rst
@@ -78,6 +78,7 @@ D-type flip-flops with asynchronous set and reset are represented by `$dffsr`
 cells. As the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition
 they also have multi-bit ``SET`` and ``CLR`` input ports and the corresponding
 polarity parameters, like `$sr` cells.
+When both set and reset are active, the state and output is undefined.
 
 D-type flip-flops with enable are represented by `$dffe`, `$adffe`, `$aldffe`,
 `$dffsre`, `$sdffe`, and `$sdffce` cells, which are enhanced variants of `$dff`,