mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-24 23:03:42 +00:00
verific->import fix for new test case
This commit is contained in:
parent
e0cef06b52
commit
3914c21286
1 changed files with 3 additions and 3 deletions
|
@ -1,4 +1,4 @@
|
||||||
verific -sv -lib <<EOF
|
import -sv -lib <<EOF
|
||||||
module TEST_CELL(input clk, input a, input b, output reg c);
|
module TEST_CELL(input clk, input a, input b, output reg c);
|
||||||
parameter PATH = "DEFAULT";
|
parameter PATH = "DEFAULT";
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
|
@ -11,14 +11,14 @@ end
|
||||||
endmodule
|
endmodule
|
||||||
EOF
|
EOF
|
||||||
|
|
||||||
verific -sv <<EOF
|
import -sv <<EOF
|
||||||
module top(input clk, input a, input b, output c, output d);
|
module top(input clk, input a, input b, output c, output d);
|
||||||
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
|
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
|
||||||
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
|
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
|
||||||
endmodule
|
endmodule
|
||||||
EOF
|
EOF
|
||||||
|
|
||||||
verific -import top
|
import -import top
|
||||||
hierarchy -top top
|
hierarchy -top top
|
||||||
stat
|
stat
|
||||||
select -assert-count 2 t:TEST_CELL
|
select -assert-count 2 t:TEST_CELL
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue