mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-15 13:28:59 +00:00
Code Activity

Add support for ffM

Browse source
This commit is contained in:
Eddie Hung 2019-08-30 15:00:56 -07:00
parent 2983a35dc0
commit 390cf34d0a
2 changed files with 48 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
passes/pmgen/xilinx_dsp.cc
View file

@ -39,6 +39,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
log("ffB: %s\n", log_id(st.ffB, "--")); log("ffB: %s\n", log_id(st.ffB, "--"));
log("dsp: %s\n", log_id(st.dsp, "--")); log("dsp: %s\n", log_id(st.dsp, "--"));
log("addAB: %s\n", log_id(st.addAB, "--")); log("addAB: %s\n", log_id(st.addAB, "--"));
log("ffM: %s\n", log_id(st.ffM, "--"));
log("ffP: %s\n", log_id(st.ffP, "--")); log("ffP: %s\n", log_id(st.ffP, "--"));
//log("muxP: %s\n", log_id(st.muxP, "--")); //log("muxP: %s\n", log_id(st.muxP, "--"));
log("sigPused: %s\n", log_signal(st.sigPused)); log("sigPused: %s\n", log_signal(st.sigPused));
@ -95,6 +96,17 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
// cell->setPort("\\CEB2", st.ffB->getPort("\\EN")); // cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
else log_abort(); else log_abort();
} }
if (st.ffM) {
SigSpec D = st.ffM->getPort("\\D");
SigSpec Q = st.ffM->getPort("\\Q");
P.replace(pm.sigmap(D), Q);
cell->setParam("\\MREG", State::S1);
if (st.ffP->type == "$dff")
cell->setPort("\\CEM", State::S1);
//else if (st.ffP->type == "$dffe")
// cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
else log_abort();
}
if (st.ffP) { if (st.ffP) {
SigSpec D; SigSpec D;
//if (st.muxP) //if (st.muxP)

39
passes/pmgen/xilinx_dsp.pmg
View file

@ -2,7 +2,7 @@ pattern xilinx_dsp
state <SigBit> clock state <SigBit> clock
state <std::set<SigBit>> sigAset sigBset state <std::set<SigBit>> sigAset sigBset
state <SigSpec> sigC sigP sigPused state <SigSpec> sigC sigM sigMused sigP sigPused
state <Cell*> addAB state <Cell*> addAB
match dsp match dsp
@ -18,6 +18,12 @@ code sigAset sigBset
sigBset = B.to_sigbit_set(); sigBset = B.to_sigbit_set();
endcode endcode
code sigM
sigM = port(dsp, \P);
//if (GetSize(sigH) <= 10)
// reject;
endcode
match ffA match ffA
if param(dsp, \AREG).as_int() == 0 if param(dsp, \AREG).as_int() == 0
if !sigAset.empty() if !sigAset.empty()
@ -63,8 +69,35 @@ code clock
} }
endcode endcode
code sigP match ffM
sigP = port(dsp, \P); if param(dsp, \MREG).as_int() == 0
select ffM->type.in($dff)
// DSP48E1 does not support clock inversion
select param(ffM, \CLK_POLARITY).as_bool()
select nusers(port(ffM, \D)) == 2
//index <SigSpec> port(ffM, \D) === sigM.extract(0, GetSize(port(ffM, \D))) // TODO: Why doesn't this work!?!
filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D)))
filter nusers(sigM.extract_end(param(ffM, \WIDTH).as_int())) == 1
optional
endmatch
code clock sigM sigP
if (ffM) {
log_warning("M FOUND!\n");
sigM = port(ffM, \Q);
for (auto b : sigM)
if (b.wire->get_bool_attribute(\keep))
reject;
SigBit c = port(ffB, \CLK).as_bit();
if (clock != SigBit() && c != clock)
reject;
clock = c;
}
sigP = sigM;
endcode endcode
match addA match addA