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Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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parent
8222c5735e
commit
390bf459fb
10 changed files with 1167 additions and 1145 deletions
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@ -99,16 +99,16 @@ struct Macc
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void from_cell(RTLIL::Cell *cell)
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{
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RTLIL::SigSpec port_a = cell->getPort("\\A");
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RTLIL::SigSpec port_a = cell->getPort(ID(A));
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ports.clear();
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bit_ports = cell->getPort("\\B");
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bit_ports = cell->getPort(ID(B));
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std::vector<RTLIL::State> config_bits = cell->getParam("\\CONFIG").bits;
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std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits;
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int config_cursor = 0;
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#ifndef NDEBUG
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int config_width = cell->getParam("\\CONFIG_WIDTH").as_int();
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int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int();
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log_assert(GetSize(config_bits) >= config_width);
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#endif
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@ -191,12 +191,12 @@ struct Macc
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port_a.append(port.in_b);
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}
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cell->setPort("\\A", port_a);
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cell->setPort("\\B", bit_ports);
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cell->setParam("\\CONFIG", config_bits);
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cell->setParam("\\CONFIG_WIDTH", GetSize(config_bits));
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cell->setParam("\\A_WIDTH", GetSize(port_a));
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cell->setParam("\\B_WIDTH", GetSize(bit_ports));
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cell->setPort(ID(A), port_a);
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cell->setPort(ID(B), bit_ports);
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cell->setParam(ID(CONFIG), config_bits);
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cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits));
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cell->setParam(ID(A_WIDTH), GetSize(port_a));
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cell->setParam(ID(B_WIDTH), GetSize(bit_ports));
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}
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bool eval(RTLIL::Const &result) const
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