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tests: remove write_ilang

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Eddie Hung 2020-04-20 15:42:29 -07:00
parent c506da3819
commit 38ee59184c
2 changed files with 0 additions and 3 deletions
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2
tests/arch/ecp5/memories.ys
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@ -208,7 +208,6 @@ select -assert-count 1 t:PDPW16KD
design -reset; read_verilog ../common/blockrom.v design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
write_ilang
synth_ecp5 -top sync_rom; cd sync_rom synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:PDPW16KD # too inefficient select -assert-count 0 t:PDPW16KD # too inefficient
select -assert-min 18 t:LUT4 select -assert-min 18 t:LUT4
@ -274,7 +273,6 @@ select -assert-count 1 t:DP16KD
design -reset; read_verilog ../common/blockrom.v design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
write_ilang
synth_ecp5 -top sync_rom; cd sync_rom synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # too inefficient select -assert-count 0 t:DP16KD # too inefficient
select -assert-min 9 t:LUT4 select -assert-min 9 t:LUT4

1
tests/arch/ice40/memories.ys
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@ -112,7 +112,6 @@ select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockrom.v design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
write_ilang
synth_ice40 -top sync_rom; cd sync_rom synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 0 t:SB_RAM40_4K # too inefficient select -assert-count 0 t:SB_RAM40_4K # too inefficient
select -assert-min 1 t:SB_LUT4 select -assert-min 1 t:SB_LUT4