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mirror of https://github.com/YosysHQ/yosys synced 2025-11-13 17:41:17 +00:00

Implement SigSpec::updhash() using a relaxed atomic for thread-safety

This commit is contained in:
Robert O'Callahan 2025-10-31 10:48:39 +00:00
parent 745222fa3b
commit 38d1d071a5
2 changed files with 66 additions and 31 deletions

View file

@ -4692,17 +4692,12 @@ void RTLIL::SigSpec::unpack()
new (&bits_) std::vector<RTLIL::SigBit>(std::move(bits));
}
void RTLIL::SigSpec::updhash() const
Hasher::hash_t RTLIL::SigSpec::updhash() const
{
RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
if (that->hash_ != 0)
return;
cover("kernel.rtlil.sigspec.hash");
Hasher h;
for (auto &c : that->chunks())
for (auto &c : chunks())
if (c.wire == NULL) {
for (auto &v : c.data)
h.eat(v);
@ -4711,9 +4706,11 @@ void RTLIL::SigSpec::updhash() const
h.eat(c.offset);
h.eat(c.width);
}
that->hash_ = h.yield();
if (that->hash_ == 0)
that->hash_ = 1;
Hasher::hash_t result = h.yield();
if (result == 0)
result = 1;
hash_.set(result);
return result;
}
void RTLIL::SigSpec::sort()
@ -4721,7 +4718,7 @@ void RTLIL::SigSpec::sort()
unpack();
cover("kernel.rtlil.sigspec.sort");
std::sort(bits_.begin(), bits_.end());
hash_ = 0;
hash_.clear();
}
void RTLIL::SigSpec::sort_and_unify()
@ -4738,7 +4735,7 @@ void RTLIL::SigSpec::sort_and_unify()
unique_bits.erase(last, unique_bits.end());
*this = unique_bits;
hash_ = 0;
hash_.clear();
}
void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
@ -4842,7 +4839,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
if (other != NULL) {
log_assert(size() == other->size());
other->unpack();
other->hash_ = 0;
other->hash_.clear();
}
for (int i = GetSize(bits_) - 1; i >= 0; i--)
@ -4859,7 +4856,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
break;
}
}
hash_ = 0;
hash_.clear();
check();
}
@ -4887,7 +4884,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
if (other != NULL) {
log_assert(size() == other->size());
other->unpack();
other->hash_ = 0;
other->hash_.clear();
}
for (int i = GetSize(bits_) - 1; i >= 0; i--) {
@ -4897,7 +4894,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
other->bits_.erase(other->bits_.begin() + i);
}
}
hash_ = 0;
hash_.clear();
check();
}
@ -4914,7 +4911,7 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
if (other != NULL) {
log_assert(size() == other->size());
other->unpack();
other->hash_ = 0;
other->hash_.clear();
}
for (int i = GetSize(bits_) - 1; i >= 0; i--) {
@ -4924,7 +4921,7 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
other->bits_.erase(other->bits_.begin() + i);
}
}
hash_ = 0;
hash_.clear();
check();
}
@ -4941,7 +4938,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *
if (other != NULL) {
log_assert(size() == other->size());
other->unpack();
other->hash_ = 0;
other->hash_.clear();
}
for (int i = GetSize(bits_) - 1; i >= 0; i--) {
@ -4951,7 +4948,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *
other->bits_.erase(other->bits_.begin() + i);
}
}
hash_ = 0;
hash_.clear();
check();
}
@ -5039,7 +5036,7 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
bits_.at(offset + i) = bit;
++i;
}
hash_ = 0;
hash_.clear();
check();
}
@ -5069,7 +5066,7 @@ void RTLIL::SigSpec::remove_const()
bits_.swap(new_bits);
}
hash_ = 0;
hash_.clear();
check();
}
@ -5085,7 +5082,7 @@ void RTLIL::SigSpec::remove(int offset, int length)
bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
hash_ = 0;
hash_.clear();
check();
}
@ -5137,7 +5134,7 @@ void RTLIL::SigSpec::rewrite_wires(std::function<void(RTLIL::Wire*& wire)> rewri
new_bits.emplace_back(c, i);
}
bits_ = std::move(new_bits);
hash_ = 0;
hash_.clear();
}
void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
@ -5152,7 +5149,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
cover("kernel.rtlil.sigspec.append");
hash_ = 0;
hash_.clear();
if (rep_ == CHUNK && signal.rep_ == CHUNK && chunk_.wire == signal.chunk_.wire) {
if (chunk_.wire == NULL) {
chunk_.data.insert(chunk_.data.end(), signal.chunk_.data.begin(), signal.chunk_.data.end());
@ -5173,7 +5170,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
{
hash_ = 0;
hash_.clear();
if (size() == 0) {
destroy();