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Make sure to apply correct signedness to loop vars.

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This commit is contained in:
nella 2026-05-13 16:52:07 +02:00
parent 2046a23a2f
commit 38c2806636
4 changed files with 112 additions and 16 deletions
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11
backends/verilog/verilog_backend.cc
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@ -456,21 +456,22 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
if (wire->attributes.count(ID::single_bit_vector))
range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
}
std::string sign = wire->is_signed ? " signed" : "";
if (wire->port_input && !wire->port_output)
f << stringf("%s" "input%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "input%s%s %s;\n", indent, sign, range, id(wire->name));
if (!wire->port_input && wire->port_output)
f << stringf("%s" "output%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "output%s%s %s;\n", indent, sign, range, id(wire->name));
if (wire->port_input && wire->port_output)
f << stringf("%s" "inout%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "inout%s%s %s;\n", indent, sign, range, id(wire->name));
if (reg_wires.count(wire->name)) {
f << stringf("%s" "reg%s %s", indent, range, id(wire->name));
f << stringf("%s" "reg%s%s %s", indent, sign, range, id(wire->name));
if (wire->attributes.count(ID::init)) {
f << stringf(" = ");
dump_const(f, wire->attributes.at(ID::init));
}
f << stringf(";\n");
} else
f << stringf("%s" "wire%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "wire%s%s %s;\n", indent, sign, range, id(wire->name));
#endif
}