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Do not require changes to cells_sim.v; try and work out comb model

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Eddie Hung 2019-10-05 22:55:18 -07:00
parent 3c6e5d82a6
commit 3879ca1398
6 changed files with 277 additions and 309 deletions
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224
techlibs/xilinx/cells_sim.v
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@ -258,33 +258,10 @@ module FDRE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
`ifdef _ABC9
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `$currQ' wire.
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) Q <= \$nextQ ;
1'b1: always @(negedge C) Q <= \$nextQ ;
1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
`endif
endmodule
(* abc9_box_id=1002, lib_whitebox, abc9_flop *)
@ -297,30 +274,7 @@ module FDRE_1 (
);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
`ifdef _ABC9
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `$currQ' wire.
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
always @(negedge C) Q <= \$nextQ ;
`endif
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
endmodule
(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
@ -341,37 +295,12 @@ module FDCE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
`ifdef _ABC9
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `$currQ' wire.
// Since this is an async flop, async behaviour is also dealt with
// using the $_ABC9_ASYNC box by abc9_map.v
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
`endif
endmodule
(* abc9_box_id=1004, lib_whitebox, abc9_flop *)
@ -384,32 +313,7 @@ module FDCE_1 (
);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
`ifdef _ABC9
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `$currQ' wire.
// Since this is an async flop, async behaviour is also dealt with
// using the $_ABC9_ASYNC box by abc9_map.v
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
`endif
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
(* abc9_box_id=1005, lib_whitebox, abc9_flop *)
@ -430,37 +334,12 @@ module FDPE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
`ifdef _ABC9
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `$currQ' wire.
// Since this is an async flop, async behaviour is also dealt with
// using the $_ABC9_ASYNC box by abc9_map.v
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
endcase endgenerate
`endif
endmodule
(* abc9_box_id=1006, lib_whitebox, abc9_flop *)
@ -473,32 +352,7 @@ module FDPE_1 (
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
`ifdef _ABC9
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `$currQ' wire.
// Since this is an async flop, async behaviour is also dealt with
// using the $_ABC9_ASYNC box by abc9_map.v
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
`endif
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
(* abc9_box_id=1007, lib_whitebox, abc9_flop *)
@ -519,33 +373,10 @@ module FDSE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
`ifdef _ABC9
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `$currQ' wire.
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) Q <= \$nextQ ;
1'b1: always @(negedge C) Q <= \$nextQ ;
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
`endif
endmodule
(* abc9_box_id=1008, lib_whitebox, abc9_flop *)
@ -558,30 +389,7 @@ module FDSE_1 (
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
`ifdef _ABC9
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `$currQ' wire.
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
always @(negedge C) Q <= \$nextQ ;
`endif
always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
endmodule
module LDCE (