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Do not require changes to cells_sim.v; try and work out comb model

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Eddie Hung 2019-10-05 22:55:18 -07:00
parent 3c6e5d82a6
commit 3879ca1398
6 changed files with 277 additions and 309 deletions
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5
techlibs/xilinx/abc9_model.v
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@ -30,11 +30,8 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
: (S0 ? I1 : I0);
endmodule
module \$__ABC_FF_ (input D, output Q);
endmodule
(* abc_box_id = 1000 *)
module \$__ABC_ASYNC (input A, S, output Y);
module \$__ABC9_ASYNC (input A, S, output Y);
endmodule
// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}