mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-15 13:28:59 +00:00
Code Activity

Add outputs before inputs to the sigmap in the AIGER backend.

Browse source
This commit is contained in:
AdamHillier 2023-04-19 11:00:51 +00:00
parent 7efc50367e
commit 3861cc31f0
1 changed files with 5 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
backends/aiger/aiger.cc
View file

@ -119,16 +119,16 @@ struct AigerWriter
if (wire->name.isPublic()) if (wire->name.isPublic())
sigmap.add(wire); sigmap.add(wire);
// promote input wires
for (auto wire : module->wires())
if (wire->port_input)
sigmap.add(wire);
// promote output wires // promote output wires
for (auto wire : module->wires()) for (auto wire : module->wires())
if (wire->port_output) if (wire->port_output)
sigmap.add(wire); sigmap.add(wire);
// promote input wires
for (auto wire : module->wires())
if (wire->port_input)
sigmap.add(wire);
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->attributes.count(ID::init)) { if (wire->attributes.count(ID::init)) {