3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-03 00:28:08 +00:00

Update tests

This commit is contained in:
Miodrag Milanovic 2024-07-24 13:29:51 +02:00
parent 262ad03cd3
commit 3848563600
10 changed files with 25 additions and 25 deletions

View file

@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module