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Update tests
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10 changed files with 25 additions and 25 deletions
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@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
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equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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