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Update tests

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This commit is contained in:
Miodrag Milanovic 2024-07-24 13:29:51 +02:00
parent 262ad03cd3
commit 3848563600
10 changed files with 25 additions and 25 deletions
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tests/arch/nanoxplore/logic.ys
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@ -1,7 +1,7 @@
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module