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https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
Various improvements in expose command (added -sep and -cut)
This commit is contained in:
Clifford Wolf
parent
b6f33576d5
commit
38469e7686
1 changed files with 117 additions and 34 deletions
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@ -208,6 +208,13 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
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}
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}
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static void add_new_wire(RTLIL::Module *module, RTLIL::Wire *wire)
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{
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if (module->count_id(wire->name))
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log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", RTLIL::id2cstr(wire->name));
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module->add(wire);
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}
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struct ExposePass : public Pass {
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ExposePass() : Pass("expose", "convert internal signals to module ports") { }
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virtual void help()
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@ -222,6 +229,10 @@ struct ExposePass : public Pass {
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log(" -dff\n");
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log(" only consider wires that are directly driven by register cell.\n");
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log("\n");
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log(" -cut\n");
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log(" when exposing a wire, create an input/output pair and cut the internal\n");
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log(" signal path at that wire.\n");
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log("\n");
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log(" -shared\n");
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log(" only expose those signals that are shared ammong the selected modules.\n");
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log(" this is useful for preparing modules for equivialence checking.\n");
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@ -233,13 +244,20 @@ struct ExposePass : public Pass {
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log(" -evert-dff\n");
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log(" turn flip-flops to sets of inputs and outputs.\n");
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log("\n");
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log(" -sep <separator>\n");
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log(" when creating new wire/port names, the original object name is suffixed\n");
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log(" with this separator (default: '.') and the port name or a type\n");
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log(" designator for the exposed signal.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_shared = false;
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bool flag_evert = false;
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bool flag_dff = false;
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bool flag_cut = false;
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bool flag_evert_dff = false;
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std::string sep = ".";
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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@ -256,14 +274,24 @@ struct ExposePass : public Pass {
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flag_dff = true;
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continue;
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}
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if (args[argidx] == "-cut") {
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flag_cut = true;
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continue;
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}
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if (args[argidx] == "-evert-dff") {
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flag_evert_dff = true;
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continue;
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}
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if (args[argidx] == "-sep" && argidx+1 < args.size()) {
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sep = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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CellTypes ct(design);
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std::map<RTLIL::Module*, std::map<std::string, dff_map_info_t>> dff_dq_maps;
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std::map<RTLIL::Module*, std::set<std::string>> dff_cells;
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@ -415,6 +443,11 @@ struct ExposePass : public Pass {
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if (flag_dff && !flag_shared)
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find_dff_wires(dff_wires, module);
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SigMap sigmap(module);
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SigMap out_to_in_map;
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std::vector<RTLIL::Wire*> new_wires;
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for (auto &it : module->wires)
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{
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if (flag_shared) {
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@ -431,9 +464,34 @@ struct ExposePass : public Pass {
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it.second->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
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}
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if (flag_cut) {
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RTLIL::Wire *in_wire = new RTLIL::Wire;
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in_wire->name = it.second->name + sep + "i";
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in_wire->width = it.second->width;
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in_wire->port_input = true;
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out_to_in_map.add(sigmap(it.second), in_wire);
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new_wires.push_back(in_wire);
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}
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}
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if (flag_cut)
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{
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for (auto it : new_wires)
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add_new_wire(module, it);
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for (auto &it : module->cells) {
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if (!ct.cell_known(it.second->type))
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continue;
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for (auto &conn : it.second->connections)
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if (ct.cell_input(it.second->type, conn.first))
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conn.second = out_to_in_map(sigmap(conn.second));
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}
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for (auto &conn : module->connections)
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conn.second = out_to_in_map(sigmap(conn.second));
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}
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SigMap sigmap(module);
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std::set<RTLIL::SigBit> set_q_bits;
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for (auto &dq : dff_dq_maps[module])
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@ -450,7 +508,7 @@ struct ExposePass : public Pass {
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RTLIL::Wire *wire_dummy_q = new RTLIL::Wire;
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wire_dummy_q->name = NEW_ID;
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wire_dummy_q->width = 0;
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module->add(wire_dummy_q);
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add_new_wire(module, wire_dummy_q);
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for (auto &cell_name : info.cells) {
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RTLIL::Cell *cell = module->cells.at(cell_name);
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@ -462,11 +520,11 @@ struct ExposePass : public Pass {
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}
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RTLIL::Wire *wire_q = new RTLIL::Wire;
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wire_q->name = wire->name + ".q";
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wire_q->name = wire->name + sep + "q";
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wire_q->width = wire->width;
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wire_q->port_input = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name));
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module->add(wire_q);
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add_new_wire(module, wire_q);
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RTLIL::SigSig connect_q;
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for (size_t i = 0; i < wire_bits_vec.size(); i++) {
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@ -479,18 +537,18 @@ struct ExposePass : public Pass {
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module->connections.push_back(connect_q);
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RTLIL::Wire *wire_d = new RTLIL::Wire;
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wire_d->name = wire->name + ".d";
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wire_d->name = wire->name + sep + "d";
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wire_d->width = wire->width;
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wire_d->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
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module->add(wire_d);
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add_new_wire(module, wire_d);
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module->connections.push_back(RTLIL::SigSig(wire_d, info.sig_d));
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RTLIL::Wire *wire_c = new RTLIL::Wire;
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wire_c->name = wire->name + ".c";
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wire_c->name = wire->name + sep + "c";
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wire_c->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
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module->add(wire_c);
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add_new_wire(module, wire_c);
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if (info.clk_polarity) {
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module->connections.push_back(RTLIL::SigSig(wire_c, info.sig_clk));
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} else {
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@ -508,10 +566,10 @@ struct ExposePass : public Pass {
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if (info.sig_arst != RTLIL::State::Sm)
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{
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RTLIL::Wire *wire_r = new RTLIL::Wire;
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wire_r->name = wire->name + ".r";
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wire_r->name = wire->name + sep + "r";
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wire_r->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
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module->add(wire_r);
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add_new_wire(module, wire_r);
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if (info.arst_polarity) {
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module->connections.push_back(RTLIL::SigSig(wire_r, info.sig_arst));
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} else {
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@ -527,11 +585,11 @@ struct ExposePass : public Pass {
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}
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RTLIL::Wire *wire_v = new RTLIL::Wire;
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wire_v->name = wire->name + ".v";
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wire_v->name = wire->name + sep + "v";
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wire_v->width = wire->width;
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wire_v->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
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module->add(wire_v);
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add_new_wire(module, wire_v);
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module->connections.push_back(RTLIL::SigSig(wire_v, info.arst_value));
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}
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}
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@ -551,33 +609,58 @@ struct ExposePass : public Pass {
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}
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RTLIL::Cell *cell = it.second;
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RTLIL::Module *mod = design->modules.at(cell->type);
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for (auto &it : mod->wires)
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if (design->modules.count(cell->type))
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{
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RTLIL::Wire *p = it.second;
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if (!p->port_input && !p->port_output)
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continue;
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RTLIL::Module *mod = design->modules.at(cell->type);
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = cell->name + "." + RTLIL::unescape_id(p->name);
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w->width = p->width;
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if (p->port_input)
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w->port_output = true;
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if (p->port_output)
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w->port_input = true;
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module->add(w);
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for (auto &it : mod->wires)
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{
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RTLIL::Wire *p = it.second;
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if (!p->port_input && !p->port_output)
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continue;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = cell->name + sep + RTLIL::unescape_id(p->name);
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w->width = p->width;
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if (p->port_input)
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w->port_output = true;
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if (p->port_output)
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w->port_input = true;
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add_new_wire(module, w);
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RTLIL::SigSpec sig;
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if (cell->connections.count(p->name) != 0)
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sig = cell->connections.at(p->name);
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sig.extend(w->width);
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if (w->port_input)
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module->connections.push_back(RTLIL::SigSig(sig, w));
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else
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module->connections.push_back(RTLIL::SigSig(w, sig));
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
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RTLIL::SigSpec sig;
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if (cell->connections.count(p->name) != 0)
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sig = cell->connections.at(p->name);
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sig.extend(w->width);
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if (w->port_input)
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module->connections.push_back(RTLIL::SigSig(sig, w));
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else
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module->connections.push_back(RTLIL::SigSig(w, sig));
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}
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}
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else
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{
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for (auto &it : cell->connections)
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{
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = cell->name + sep + RTLIL::unescape_id(it.first);
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w->width = it.second.width;
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if (ct.cell_input(cell->type, it.first))
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w->port_output = true;
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if (ct.cell_output(cell->type, it.first))
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w->port_input = true;
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add_new_wire(module, w);
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
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if (w->port_input)
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module->connections.push_back(RTLIL::SigSig(it.second, w));
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else
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module->connections.push_back(RTLIL::SigSig(w, it.second));
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}
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}
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delete_cells.push_back(cell->name);
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