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Add test

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This commit is contained in:
Eddie Hung 2019-07-19 12:43:02 -07:00
parent 25ff27e37f
commit 3839bd50f2
1 changed files with 22 additions and 0 deletions
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tests/various/wreduce.ys Normal file
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read_verilog <<EOT
module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o);
assign o = (i << 4) + j;
endmodule
EOT
hierarchy -top wreduce_add_test
proc
design -save gold
prep
select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter