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Merge pull request #2872 from whitequark/cxxrtl-fix-2521

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cxxrtl: don't expect user cell inputs to be wires
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whitequark 2021-07-16 10:34:30 +00:00 committed by GitHub
parent 10c3214e56 b28ca7f5ac
commit 37f5ed9439
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GPG key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 2 deletions
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4
backends/cxxrtl/cxxrtl_backend.cc
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@ -1295,7 +1295,7 @@ struct CxxrtlWorker {
for (auto conn : cell->connections()) for (auto conn : cell->connections())
if (cell->input(conn.first)) { if (cell->input(conn.first)) {
RTLIL::Module *cell_module = cell->module->design->module(cell->type); RTLIL::Module *cell_module = cell->module->design->module(cell->type);
log_assert(cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()); log_assert(cell_module != nullptr && cell_module->wire(conn.first));
RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first); RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first);
f << indent << mangle(cell) << access << mangle_wire_name(conn.first); f << indent << mangle(cell) << access << mangle_wire_name(conn.first);
if (!is_cxxrtl_blackbox_cell(cell) && wire_types[cell_module_wire].is_buffered()) { if (!is_cxxrtl_blackbox_cell(cell) && wire_types[cell_module_wire].is_buffered()) {
@ -1305,7 +1305,7 @@ struct CxxrtlWorker {
f << " = "; f << " = ";
dump_sigspec_rhs(conn.second); dump_sigspec_rhs(conn.second);
f << ";\n"; f << ";\n";
if (getenv("CXXRTL_VOID_MY_WARRANTY")) { if (getenv("CXXRTL_VOID_MY_WARRANTY") && conn.second.is_wire()) {
// Until we have proper clock tree detection, this really awful hack that opportunistically // Until we have proper clock tree detection, this really awful hack that opportunistically
// propagates prev_* values for clocks can be used to estimate how much faster a design could // propagates prev_* values for clocks can be used to estimate how much faster a design could
// be if only one clock edge was simulated by replacing: // be if only one clock edge was simulated by replacing: