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Merge pull request #1845 from YosysHQ/eddie/kernel_speedup

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kernel: speedup by using more pass-by-const-ref
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Eddie Hung 2020-04-02 07:13:33 -07:00 • committed by GitHub
commit 37f42fe102
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20 changed files with 538 additions and 560 deletions
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16
passes/sat/clk2fflogic.cc
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@ -117,11 +117,11 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge_pattern;
if (clkpol) {
clock_edge_pattern.append_bit(State::S0);
clock_edge_pattern.append_bit(State::S1);
clock_edge_pattern.append(State::S0);
clock_edge_pattern.append(State::S1);
} else {
clock_edge_pattern.append_bit(State::S1);
clock_edge_pattern.append_bit(State::S0);
clock_edge_pattern.append(State::S1);
clock_edge_pattern.append(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
@ -257,11 +257,11 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge_pattern;
if (clkpol) {
clock_edge_pattern.append_bit(State::S0);
clock_edge_pattern.append_bit(State::S1);
clock_edge_pattern.append(State::S0);
clock_edge_pattern.append(State::S1);
} else {
clock_edge_pattern.append_bit(State::S1);
clock_edge_pattern.append_bit(State::S0);
clock_edge_pattern.append(State::S1);
clock_edge_pattern.append(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);