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Progress in presentation

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Clifford Wolf 2014-02-16 22:31:53 +01:00
parent 6d63f39eb6
commit 37cbb1ca60
5 changed files with 80 additions and 1 deletions
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5
manual/PRESENTATION_ExAdv/Makefile
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@ -1,5 +1,5 @@
all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf
all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf
select_01.pdf: select_01.v select_01.ys
../../yosys select_01.ys
@ -13,3 +13,6 @@ sym_mul.pdf: sym_mul_*
mymul.pdf: mymul_*
../../yosys mymul_test.ys
mulshift.pdf: mulshift_*
../../yosys mulshift_test.ys

26
manual/PRESENTATION_ExAdv/mulshift_map.v Normal file
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module MYMUL(A, B, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output reg [WIDTH-1:0] Y;
parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
reg _TECHMAP_FAIL_;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
integer i;
always @* begin
_TECHMAP_FAIL_ <= 1;
for (i = 0; i < WIDTH; i=i+1) begin
if (_TECHMAP_CONSTVAL_A_ === WIDTH'd1 << i) begin
_TECHMAP_FAIL_ <= 0;
Y <= B << i;
end
if (_TECHMAP_CONSTVAL_B_ === WIDTH'd1 << i) begin
_TECHMAP_FAIL_ <= 0;
Y <= A << i;
end
end
end
endmodule

5
manual/PRESENTATION_ExAdv/mulshift_test.v Normal file
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module test (A, X, Y);
input [7:0] A;
output [7:0] X = A * 8'd 6;
output [7:0] Y = A * 8'd 8;
endmodule

7
manual/PRESENTATION_ExAdv/mulshift_test.ys Normal file
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read_verilog mulshift_test.v
hierarchy -check -top test
techmap -map sym_mul_map.v \
-map mulshift_map.v;;
show -prefix mulshift -format pdf -notitle -lib sym_mul_cells.v