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Add another test

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This commit is contained in:
Eddie Hung 2019-12-16 13:57:55 -08:00
parent 4158ce4eda
commit 378d9e6e0c
1 changed files with 8 additions and 1 deletions
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9
tests/arch/xilinx/blockram.ys
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@ -84,7 +84,14 @@ design -reset
read_verilog ../common/blockram.v read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory setattr -set ram_style "block" m:memory
dump m:* synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
setattr -set ram_block 1 m:memory
synth_xilinx -top sync_ram_sdp synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1 select -assert-count 1 t:RAMB18E1