mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Added read_verilog -icells option

Browse source
This commit is contained in:
Clifford Wolf 2014-01-29 00:59:28 +01:00
parent a86f33653d
commit 375c4dddc1
4 changed files with 20 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
frontends/ast/genrtlil.cc
View file

@ -1334,6 +1334,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
AstNode *child = *it;
if (child->type == AST_CELLTYPE) {
cell->type = child->str;
if (flag_icells && cell->type.substr(0, 2) == "\\$")
cell->type = cell->type.substr(1);
continue;
}
if (child->type == AST_PARASET) {