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Merge 365c144a3d into 5aa9bfbf7d

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KrystalDelusion 2025-05-09 09:06:25 +12:00 • committed by GitHub
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34
.github/workflows/test-build.yml vendored
View file

@ -158,6 +158,40 @@ jobs:
run: | run: |
find tests/**/*.err -print -exec cat {} \; find tests/**/*.err -print -exec cat {} \;
test-cells:
name: Run test_cell
runs-on: ubuntu-latest
needs: [build-yosys, pre_job]
if: needs.pre_job.outputs.should_skip != 'true'
env:
CC: clang
steps:
- name: Checkout Yosys
uses: actions/checkout@v4
with:
persist-credentials: false
- name: Setup environment
uses: ./.github/actions/setup-build-env
- name: Download build artifact
uses: actions/download-artifact@v4
with:
name: build-ubuntu-latest
- name: Uncompress build
shell: bash
run:
tar -xvf build.tar
- name: test_cell
shell: bash
run: |
./yosys -p 'test_cell all'
./yosys -p 'test_cell -nosat -aigmap $pow $pmux'
./yosys -p 'test_cell -nosat -aigmap $eqx $nex $bweqx'
./yosys -p 'test_cell -aigmap $buf'
test-docs: test-docs:
name: Run docs tests name: Run docs tests
runs-on: ${{ matrix.os }} runs-on: ${{ matrix.os }}

6
kernel/celltypes.h
View file

@ -334,6 +334,7 @@ struct CellTypes
return v; return v;
} }
// Consider using the ConstEval struct instead if you need named ports and/or multiple outputs
static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr) static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)
{ {
if (type == ID($sshr) && !signed1) if (type == ID($sshr) && !signed1)
@ -416,6 +417,7 @@ struct CellTypes
log_abort(); log_abort();
} }
// Consider using the ConstEval struct instead if you need named ports and/or multiple outputs
static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr) static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
{ {
if (cell->type == ID($slice)) { if (cell->type == ID($slice)) {
@ -503,10 +505,13 @@ struct CellTypes
return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp); return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
} }
// Consider using the ConstEval struct instead if you need named ports and/or multiple outputs
static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr) static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)
{ {
if (cell->type.in(ID($mux), ID($_MUX_))) if (cell->type.in(ID($mux), ID($_MUX_)))
return const_mux(arg1, arg2, arg3); return const_mux(arg1, arg2, arg3);
if (cell->type == ID($_NMUX_))
return eval_not(const_mux(arg1, arg2, arg3));
if (cell->type == ID($bwmux)) if (cell->type == ID($bwmux))
return const_bwmux(arg1, arg2, arg3); return const_bwmux(arg1, arg2, arg3);
if (cell->type == ID($pmux)) if (cell->type == ID($pmux))
@ -520,6 +525,7 @@ struct CellTypes
return eval(cell, arg1, arg2, errp); return eval(cell, arg1, arg2, errp);
} }
// Consider using the ConstEval struct instead if you need named ports and/or multiple outputs
static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr) static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)
{ {
if (cell->type == ID($_AOI4_)) if (cell->type == ID($_AOI4_))

6
kernel/consteval.h
View file

@ -349,7 +349,11 @@ struct ConstEval
return false; return false;
bool eval_err = false; bool eval_err = false;
RTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err); RTLIL::Const eval_ret;
if (sig_s.size() > 0 && eval(sig_s, undef, cell)) {
eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_s.as_const(), &eval_err);
} else
eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);
if (eval_err) if (eval_err)
return false; return false;

6
kernel/rtlil.cc
View file

@ -4242,9 +4242,9 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:")) type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
return; return;
if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux)) { if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux) || type == ID($bwmux) || type == ID($bweqx)) {
parameters[ID::WIDTH] = GetSize(connections_[ID::Y]); parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
if (type != ID($buf) && type != ID($mux)) if (type.in(ID($pmux), ID($bmux)))
parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]); parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
check(); check();
return; return;
@ -4299,7 +4299,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]); parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
} }
if (connections_.count(ID::Y)) if (connections_.count(ID::Y) && type != ID($concat))
parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]); parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
if (connections_.count(ID::Q)) if (connections_.count(ID::Q))

165
passes/tests/test_cell.cc
View file

@ -71,6 +71,29 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
cell->setPort(ID::Y, wire); cell->setPort(ID::Y, wire);
} }
if (cell_type.in(ID($_MUX_), ID($_NMUX_)))
{
wire = module->addWire(ID::A);
wire->width = 1;
wire->port_input = true;
cell->setPort(ID::A, wire);
wire = module->addWire(ID::B);
wire->width = 1;
wire->port_input = true;
cell->setPort(ID::B, wire);
wire = module->addWire(ID::S);
wire->width = 1;
wire->port_input = true;
cell->setPort(ID::S, wire);
wire = module->addWire(ID::Y);
wire->width = 1;
wire->port_output = true;
cell->setPort(ID::Y, wire);
}
if (cell_type == ID($bmux)) if (cell_type == ID($bmux))
{ {
int width = 1 + xorshift32(8 * bloat_factor); int width = 1 + xorshift32(8 * bloat_factor);
@ -167,7 +190,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
cell->setPort(ID::CO, wire); cell->setPort(ID::CO, wire);
} }
if (cell_type == ID($macc)) if (cell_type == ID($macc_v2))
{ {
Macc macc; Macc macc;
int width = 1 + xorshift32(8 * bloat_factor); int width = 1 + xorshift32(8 * bloat_factor);
@ -201,6 +224,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
this_term.do_subtract = xorshift32(2) == 1; this_term.do_subtract = xorshift32(2) == 1;
macc.terms.push_back(this_term); macc.terms.push_back(this_term);
} }
// Macc::to_cell sets the input ports // Macc::to_cell sets the input ports
macc.to_cell(cell); macc.to_cell(cell);
@ -208,12 +232,6 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
wire->width = width; wire->width = width;
wire->port_output = true; wire->port_output = true;
cell->setPort(ID::Y, wire); cell->setPort(ID::Y, wire);
// override the B input (macc helpers always sets an empty vector)
wire = module->addWire(ID::B);
wire->width = xorshift32(mulbits_a ? xorshift32(4)+1 : xorshift32(16)+1);
wire->port_input = true;
cell->setPort(ID::B, wire);
} }
if (cell_type == ID($lut)) if (cell_type == ID($lut))
@ -273,6 +291,9 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
if (cell_type_flags.find('A') != std::string::npos) { if (cell_type_flags.find('A') != std::string::npos) {
wire = module->addWire(ID::A); wire = module->addWire(ID::A);
if (cell_type_flags.find('b') != std::string::npos)
wire->width = 1;
else
wire->width = 1 + xorshift32(8 * bloat_factor); wire->width = 1 + xorshift32(8 * bloat_factor);
wire->port_input = true; wire->port_input = true;
cell->setPort(ID::A, wire); cell->setPort(ID::A, wire);
@ -280,7 +301,9 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
if (cell_type_flags.find('B') != std::string::npos) { if (cell_type_flags.find('B') != std::string::npos) {
wire = module->addWire(ID::B); wire = module->addWire(ID::B);
if (cell_type_flags.find('h') != std::string::npos) if (cell_type_flags.find('b') != std::string::npos)
wire->width = 1;
else if (cell_type_flags.find('h') != std::string::npos)
wire->width = 1 + xorshift32(6 * bloat_factor); wire->width = 1 + xorshift32(6 * bloat_factor);
else else
wire->width = 1 + xorshift32(8 * bloat_factor); wire->width = 1 + xorshift32(8 * bloat_factor);
@ -288,6 +311,26 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
cell->setPort(ID::B, wire); cell->setPort(ID::B, wire);
} }
if (cell_type_flags.find('C') != std::string::npos) {
wire = module->addWire(ID::C);
if (cell_type_flags.find('b') != std::string::npos)
wire->width = 1;
else
wire->width = 1 + xorshift32(8 * bloat_factor);
wire->port_input = true;
cell->setPort(ID::C, wire);
}
if (cell_type_flags.find('D') != std::string::npos) {
wire = module->addWire(ID::D);
if (cell_type_flags.find('b') != std::string::npos)
wire->width = 1;
else
wire->width = 1 + xorshift32(8 * bloat_factor);
wire->port_input = true;
cell->setPort(ID::D, wire);
}
if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) { if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
if (cell_type_flags.find('A') != std::string::npos) if (cell_type_flags.find('A') != std::string::npos)
cell->parameters[ID::A_SIGNED] = true; cell->parameters[ID::A_SIGNED] = true;
@ -304,6 +347,9 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
if (cell_type_flags.find('Y') != std::string::npos) { if (cell_type_flags.find('Y') != std::string::npos) {
wire = module->addWire(ID::Y); wire = module->addWire(ID::Y);
if (cell_type_flags.find('b') != std::string::npos)
wire->width = 1;
else
wire->width = 1 + xorshift32(8 * bloat_factor); wire->width = 1 + xorshift32(8 * bloat_factor);
wire->port_output = true; wire->port_output = true;
cell->setPort(ID::Y, wire); cell->setPort(ID::Y, wire);
@ -345,6 +391,58 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
cell->setPort(ID::CO, wire); cell->setPort(ID::CO, wire);
} }
if (cell_type == ID($slice))
{
int a_size = GetSize(cell->getPort(ID::A));
int y_size = 1;
if (a_size > 1)
y_size += (xorshift32(8 * bloat_factor) % (a_size - 1));
wire = module->addWire(ID::Y);
wire->width = y_size;
wire->port_output = true;
cell->setPort(ID::Y, wire);
if (a_size > y_size)
cell->setParam(ID::OFFSET, (xorshift32(8 * bloat_factor) % (a_size - y_size)));
else
cell->setParam(ID::OFFSET, 0);
}
if (cell_type == ID($concat))
{
wire = module->addWire(ID::Y);
wire->width = GetSize(cell->getPort(ID::A)) + GetSize(cell->getPort(ID::B));
wire->port_output = true;
cell->setPort(ID::Y, wire);
}
if (cell_type == ID($buf))
{
wire = module->addWire(ID::Y);
wire->width = GetSize(cell->getPort(ID::A));
wire->port_output = true;
cell->setPort(ID::Y, wire);
}
if (cell_type.in(ID($bwmux), ID($bweqx)))
{
int a_size = GetSize(cell->getPort(ID::A));
wire = module->addWire(ID::B);
wire->width = a_size;
wire->port_input = true;
cell->setPort(ID::B, wire);
if (cell_type == ID($bwmux))
{
wire = module->addWire(ID::S);
wire->width = a_size;
wire->port_input = true;
cell->setPort(ID::S, wire);
}
wire = module->addWire(ID::Y);
wire->width = a_size;
wire->port_output = true;
cell->setPort(ID::Y, wire);
}
if (constmode) if (constmode)
{ {
auto conn_list = cell->connections(); auto conn_list = cell->connections();
@ -882,6 +980,9 @@ struct TestCellPass : public Pass {
cell_types[ID($not)] = "ASY"; cell_types[ID($not)] = "ASY";
cell_types[ID($pos)] = "ASY"; cell_types[ID($pos)] = "ASY";
cell_types[ID($neg)] = "ASY"; cell_types[ID($neg)] = "ASY";
// $buf is unsupported with techmap -assert
if (techmap_cmd.compare("techmap -assert") != 0)
cell_types[ID($buf)] = "A";
cell_types[ID($and)] = "ABSY"; cell_types[ID($and)] = "ABSY";
cell_types[ID($or)] = "ABSY"; cell_types[ID($or)] = "ABSY";
@ -905,8 +1006,14 @@ struct TestCellPass : public Pass {
cell_types[ID($le)] = "ABSY"; cell_types[ID($le)] = "ABSY";
cell_types[ID($eq)] = "ABSY"; cell_types[ID($eq)] = "ABSY";
cell_types[ID($ne)] = "ABSY"; cell_types[ID($ne)] = "ABSY";
// cell_types[ID($eqx)] = "ABSY"; // $eqx, $nex, and $bweqx don't work in sat, and are unsupported with
// cell_types[ID($nex)] = "ABSY"; // 'techmap -assert'
if (nosat && techmap_cmd.compare("techmap -assert") != 0)
{
cell_types[ID($eqx)] = "ABSY";
cell_types[ID($nex)] = "ABSY";
cell_types[ID($bweqx)] = "A";
}
cell_types[ID($ge)] = "ABSY"; cell_types[ID($ge)] = "ABSY";
cell_types[ID($gt)] = "ABSY"; cell_types[ID($gt)] = "ABSY";
@ -917,7 +1024,10 @@ struct TestCellPass : public Pass {
cell_types[ID($mod)] = "ABSY"; cell_types[ID($mod)] = "ABSY";
cell_types[ID($divfloor)] = "ABSY"; cell_types[ID($divfloor)] = "ABSY";
cell_types[ID($modfloor)] = "ABSY"; cell_types[ID($modfloor)] = "ABSY";
// cell_types[ID($pow)] = "ABsY"; // $pow doesnt work in sat, not supported with 'techmap -assert', and only
// only partially supported with '-simlib'
if (nosat && techmap_cmd.compare("aigmap") == 0)
cell_types[ID($pow)] = "ABsY";
cell_types[ID($logic_not)] = "ASY"; cell_types[ID($logic_not)] = "ASY";
cell_types[ID($logic_and)] = "ABSY"; cell_types[ID($logic_and)] = "ABSY";
@ -926,20 +1036,43 @@ struct TestCellPass : public Pass {
cell_types[ID($mux)] = "*"; cell_types[ID($mux)] = "*";
cell_types[ID($bmux)] = "*"; cell_types[ID($bmux)] = "*";
cell_types[ID($demux)] = "*"; cell_types[ID($demux)] = "*";
if (edges) { // $pmux doesn't work in sat, and is not supported with 'techmap -assert' or
// '-simlib'
if (nosat && techmap_cmd.compare("aigmap") == 0)
cell_types[ID($pmux)] = "*"; cell_types[ID($pmux)] = "*";
} cell_types[ID($bwmux)] = "A";
// cell_types[ID($slice)] = "A"; cell_types[ID($slice)] = "A";
// cell_types[ID($concat)] = "A"; cell_types[ID($concat)] = "AB";
cell_types[ID($lut)] = "*"; cell_types[ID($lut)] = "*";
cell_types[ID($sop)] = "*"; cell_types[ID($sop)] = "*";
cell_types[ID($alu)] = "ABSY"; cell_types[ID($alu)] = "ABSY";
cell_types[ID($lcu)] = "*"; cell_types[ID($lcu)] = "*";
cell_types[ID($macc)] = "*"; cell_types[ID($macc_v2)] = "*";
cell_types[ID($fa)] = "*"; cell_types[ID($fa)] = "*";
cell_types[ID($_BUF_)] = "AYb";
cell_types[ID($_NOT_)] = "AYb";
cell_types[ID($_AND_)] = "ABYb";
cell_types[ID($_NAND_)] = "ABYb";
cell_types[ID($_OR_)] = "ABYb";
cell_types[ID($_NOR_)] = "ABYb";
cell_types[ID($_XOR_)] = "ABYb";
cell_types[ID($_XNOR_)] = "ABYb";
cell_types[ID($_ANDNOT_)] = "ABYb";
cell_types[ID($_ORNOT_)] = "ABYb";
cell_types[ID($_MUX_)] = "*";
cell_types[ID($_NMUX_)] = "*";
// wide $_MUX_ cells are not yet implemented
// cell_types[ID($_MUX4_)] = "*";
// cell_types[ID($_MUX8_)] = "*";
// cell_types[ID($_MUX16_)] = "*";
cell_types[ID($_AOI3_)] = "ABCYb";
cell_types[ID($_OAI3_)] = "ABCYb";
cell_types[ID($_AOI4_)] = "ABCDYb";
cell_types[ID($_OAI4_)] = "ABCDYb";
for (; argidx < GetSize(args); argidx++) for (; argidx < GetSize(args); argidx++)
{ {
if (args[argidx].rfind("-", 0) == 0) if (args[argidx].rfind("-", 0) == 0)