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Merge remote-tracking branch 'origin/master' into xc7dsp

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This commit is contained in:
Eddie Hung 2019-09-04 12:37:42 -07:00
commit 3732d421c5
12 changed files with 87 additions and 24 deletions
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13
techlibs/ecp5/cells_sim.v
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@ -229,14 +229,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter REGSET = "RESET";
parameter [127:0] LSRMODE = "LSR";
reg muxce;
always @(*)
wire muxce;
generate
case (CEMUX)
"1": muxce = 1'b1;
"0": muxce = 1'b0;
"INV": muxce = ~CE;
default: muxce = CE;
"1": assign muxce = 1'b1;
"0": assign muxce = 1'b0;
"INV": assign muxce = ~CE;
default: assign muxce = CE;
endcase
endgenerate
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;

2
techlibs/ecp5/ecp5_gsr.cc
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@ -124,7 +124,7 @@ struct Ecp5GsrPass : public Pass {
SigBit lsr = sigmap(sig_lsr[0]);
if (!inverted_gsr.count(lsr))
continue;
cell->setParam(ID(SRMODE), Const("SYNC"));
cell->setParam(ID(SRMODE), Const("LSR_OVER_CE"));
cell->unsetPort(ID(LSR));
}