mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-22 19:17:55 +00:00
Merge remote-tracking branch 'origin/master' into xc7dsp
This commit is contained in:
commit
3732d421c5
12 changed files with 87 additions and 24 deletions
|
@ -664,7 +664,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
|
|||
} else
|
||||
if (arg == "%D") {
|
||||
if (work_stack.size() < 2)
|
||||
log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
|
||||
log_cmd_error("Must have at least two elements on the stack for operator %%D.\n");
|
||||
select_op_diff(design, work_stack[work_stack.size()-1], work_stack[work_stack.size()-2]);
|
||||
work_stack[work_stack.size()-2] = work_stack[work_stack.size()-1];
|
||||
work_stack.pop_back();
|
||||
|
@ -693,7 +693,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
|
|||
} else
|
||||
if (arg == "%C") {
|
||||
if (work_stack.size() < 1)
|
||||
log_cmd_error("Must have at least one element on the stack for operator %%M.\n");
|
||||
log_cmd_error("Must have at least one element on the stack for operator %%C.\n");
|
||||
select_op_module_to_cells(design, work_stack[work_stack.size()-1]);
|
||||
} else
|
||||
if (arg == "%c") {
|
||||
|
|
|
@ -808,6 +808,30 @@ struct HierarchyPass : public Pass {
|
|||
if (mod_it.second->get_bool_attribute("\\top"))
|
||||
top_mod = mod_it.second;
|
||||
|
||||
if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
|
||||
IdString top_name = top_mod->name.substr(strlen("$abstract"));
|
||||
|
||||
dict<RTLIL::IdString, RTLIL::Const> top_parameters;
|
||||
for (auto ¶ : parameters) {
|
||||
SigSpec sig_value;
|
||||
if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second))
|
||||
log_cmd_error("Can't decode value '%s'!\n", para.second.c_str());
|
||||
top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const();
|
||||
}
|
||||
|
||||
top_mod = design->module(top_mod->derive(design, top_parameters));
|
||||
|
||||
if (top_mod != nullptr && top_mod->name != top_name) {
|
||||
Module *m = top_mod->clone();
|
||||
m->name = top_name;
|
||||
Module *old_mod = design->module(top_name);
|
||||
if (old_mod)
|
||||
design->remove(old_mod);
|
||||
design->add(m);
|
||||
top_mod = m;
|
||||
}
|
||||
}
|
||||
|
||||
if (top_mod == nullptr && auto_top_mode) {
|
||||
log_header(design, "Finding top of design hierarchy..\n");
|
||||
dict<Module*, int> db;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue