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Add Liberty to verilog conversion tests

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This commit is contained in:
Akash Levy 2024-10-05 01:34:12 -10:00
parent 4de5e718ed
commit 36e57017fe
8 changed files with 239 additions and 0 deletions
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tests/liberty_verilog/busdef2.lib.v.ok Normal file
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(* blackbox = 1 *)
(* leakage_power_unit = "1pW" *)
module not_cell(A, Y);
input [7:0] A;
wire [7:0] A;
output Y;
wire Y;
endmodule