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Add Liberty to verilog conversion tests

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This commit is contained in:
Akash Levy 2024-10-05 01:34:12 -10:00
parent 4de5e718ed
commit 36e57017fe
8 changed files with 239 additions and 0 deletions
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tests/liberty_verilog/busdef.lib.v.ok Normal file
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(* area = "1" *)
(* blackbox = 1 *)
module SRAM(CE1, I1);
input CE1;
wire CE1;
input [3:0] I1;
wire [3:0] I1;
endmodule