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Add Liberty to verilog conversion tests

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This commit is contained in:
Akash Levy 2024-10-05 01:34:12 -10:00
parent 4de5e718ed
commit 36e57017fe
8 changed files with 239 additions and 0 deletions
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tests/liberty_verilog/bundledef.lib.v.ok Normal file
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(* LeakagePower = "8" *)
(* area = "16" *)
(* blackbox = 1 *)
module inv(Z0, Z1, Z2, Z3, D0, D1, D2, D3);
input D0;
wire D0;
input D1;
wire D1;
input D2;
wire D2;
input D3;
wire D3;
output Z0;
wire Z0;
output Z1;
wire Z1;
output Z2;
wire Z2;
output Z3;
wire Z3;
endmodule