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Extend test for RSTP and RSTM

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This commit is contained in:
Eddie Hung 2019-09-11 09:09:08 -07:00
parent ded805ae5d
commit 36d6db7f8a
2 changed files with 50 additions and 3 deletions
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17
tests/xilinx/macc.ys
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@ -1,6 +1,8 @@
read_verilog macc.v
design -save read
proc
hierarchy -auto-top
hierarchy -top macc
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
miter -equiv -flatten -make_assert -make_outputs gold gate miter
@ -11,3 +13,16 @@ select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
design -load read
proc
hierarchy -top macc2
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc2 # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:DSP48E1 %% t:* %D