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@ -135,6 +135,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
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module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
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module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
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// Reset logic is optional in AIGER 1.9
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if (f.peek() == ' ') {
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if (f.peek() == ' ') {
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if (!(f >> l3))
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if (!(f >> l3))
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log_error("Line %d cannot be interpreted as a latch!\n", line_count);
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log_error("Line %d cannot be interpreted as a latch!\n", line_count);
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