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Added RTLIL and Liberty syntax highlighting to manual

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Clifford Wolf 2013-07-25 14:00:16 +02:00
parent 88d0829d65
commit 36c39cbd04
3 changed files with 19 additions and 4 deletions
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manual/CHAPTER_Verilog.tex
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@ -533,7 +533,7 @@ end
This is translated by the Verilog and AST frontends into the following RTLIL code (attributes, cell parameters
and wire declarations not included):
\begin{lstlisting}[numbers=left,frame=single]
\begin{lstlisting}[numbers=left,frame=single,language=rtlil]
cell $logic_not $logic_not$<input>:4$2
connect \A \in1
connect \Y $logic_not$<input>:4$2_Y