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start implementing support for intel le based logic devices

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This commit is contained in:
Artur Swiderski 2020-10-10 19:08:54 +02:00
parent c403c984dd
commit 36bd075865
34 changed files with 3058 additions and 0 deletions
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60
tests/arch/intel_le/mul.ys Normal file
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read_verilog ../common/mul.v
chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
hierarchy -top top
proc
equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_MUL9X9
select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
# Cyclone 10 GX does not have 9x9 multipliers.
design -reset
read_verilog ../common/mul.v
chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
hierarchy -top top
proc
equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_MUL18X18
select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
design -reset
read_verilog ../common/mul.v
chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
hierarchy -top top
proc
equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclone10gx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_MUL18X18
select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
design -reset
read_verilog ../common/mul.v
chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
hierarchy -top top
proc
equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_MUL27X27
select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
design -reset
read_verilog ../common/mul.v
chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
hierarchy -top top
proc
equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclone10gx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_MUL27X27
select -assert-none t:MISTRAL_MUL27X27 %% t:* %D