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start implementing support for intel le based logic devices

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This commit is contained in:
Artur Swiderski 2020-10-10 19:08:54 +02:00
parent c403c984dd
commit 36bd075865
34 changed files with 3058 additions and 0 deletions
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18
tests/arch/intel_le/add_sub.ys Normal file
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read_verilog ../common/add_sub.v
hierarchy -top top
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
design -reset
read_verilog ../common/add_sub.v
hierarchy -top top
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D